Datasheet > AD9550BCPZ-REEL7

AD9550BCPZ-REEL7

更新时间： 2024-01-23 05:51:37

品牌	Logo	应用领域
亚德诺 - ADI		通信时钟
页数	文件大小	规格书
20页	393K
描述
Integer-N Clock Translator for Wireline Communications

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AD9550BCPZ-REEL7 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFN
包装说明：	HVQCCN, LCC32,.2SQ,20	针数：	32
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.77
应用程序：	SONET;SDH	JESD-30 代码：	S-XQCC-N32
JESD-609代码：	e3	长度：	5 mm
湿度敏感等级：	1	功能数量：	1
端子数量：	32	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装等效代码：	LCC32,.2SQ,20
封装形状：	SQUARE	封装形式：	CHIP CARRIER
峰值回流温度（摄氏度）：	260	电源：	3.3 V
认证状态：	Not Qualified	座面最大高度：	0.8 mm
子类别：	Other Telecom ICs	最大压摆率：	0.185 mA
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	电信集成电路类型：	ATM/SONET/SDH SUPPORT CIRCUIT
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	5 mm	Base Number Matches：	1

AD9550BCPZ-REEL7 数据手册

Integer-N Clock Translator

for Wireline Communications

AD9550

BASIC BLOCK DIAGRAM

FEATURES

Converts preset standard input frequencies to standard

output frequencies

Input frequencies from 8 kHz to 200 MHz

Output frequencies up to 810 MHz LVPECL and LVDS

(200 MHz CMOS)

OUT2

OUT1

OUTPUT

CIRCUITRY

PLL

REF

Preset pin-programmable frequency translation ratios

On-chip VCO

PIN DECODER

Single-ended CMOS reference input

Two output clocks (independently programmable as LVDS,

LVPECL, or CMOS)

AD9550

Figure 1.

Single supply (3.3 V)

Very low power: <450 mW (under most conditions)

Small package size (5 mm × 5 mm)

Exceeds Telcordia GR-253-CORE jitter generation, transfer

and tolerance specifications

APPLICATIONS

Cost effective replacement of high frequency VCXO, OCXO,

and SAW resonators

Flexible frequency translation for wireline applications such

as Ethernet, T1/E1, SONET/SDH, GPON, xDSL

Wireless infrastructure

Test and measurement (including handheld devices)

GENERAL DESCRIPTION

The AD9550 is a phase-locked loop (PLL) based clock translator

designed to address the needs of wireline communication and

base station applications. The device employs an integer-N PLL

to accommodate the applicable frequency translation requirements.

It accepts a single-ended input reference signal at the REF input.

15 possible input frequencies to a list of 52 possible output

frequency pairs (OUT1 and OUT2).

The AD9550 output is compatible with LVPECL, LVDS, or

single-ended CMOS logic levels, although the AD9550 is

implemented in a strictly CMOS process.

The AD9550 is pin programmable, providing a matrix of

standard input/output frequency translations from a list of

The AD9550 operates over the extended industrial temperature

range of −40°C to +85°C.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rightsof third parties that may result fromits use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

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