Dual Input Multiservice
Line Card Adaptive Clock Translator
AD9557
Data Sheet
Pin program function for easy frequency translation
FEATURES
configuration
Software controlled power-down
40-lead, 6 mm × 6 mm, LFCSP package
Supports GR-1244 Stratum 3 stability in holdover mode
Supports smooth reference switchover with virtually
no disturbance on output phase
Supports Telcordia GR-253 jitter generation, transfer, and
tolerance for SONET/SDH up to OC-192 systems
Supports ITU-T G.8262 synchronous Ethernet slave clocks
Supports ITU-T G.823, G.824, G.825, and G.8261
Auto/manual holdover and reference switchover
2 reference inputs (single-ended or differential)
Input reference frequencies: 2 kHz to 1250 MHz
Reference validation and frequency monitoring (1 ppm)
Programmable input reference switchover priority
20-bit programmable input reference divider
2 pairs of clock output pins, with each pair configurable as
a single differential LVDS/HSTL output or as 2 single-ended
CMOS outputs
Output frequencies: 360 kHz to 1250 MHz
Programmable 17-bit integer and 24-bit fractional
feedback divider in digital PLL
Programmable digital loop filter covering loop bandwidths
from 0.1 Hz to 5 kHz (2 kHz maximum for <0.1 dB of peaking)
Low noise system clock multiplier
APPLICATIONS
Network synchronization, including synchronous Ethernet
and SDH to OTN mapping/demapping
Cleanup of reference clock jitter
SONET/SDH clocks up to OC-192, including FEC
Stratum 3 holdover, jitter cleanup, and phase transient control
Wireless base station controllers
Cable infrastructure
Data communications
GENERAL DESCRIPTION
The AD9557 is a low loop bandwidth clock multiplier that
provides jitter cleanup and synchronization for many systems,
including synchronous optical networks (SONET/SDH). The
AD9557 generates an output clock synchronized to up to four
external input references. The digital PLL allows for reduction
of input time jitter or phase noise associated with the external
references. The digitally controlled loop and holdover circuitry
of the AD9557 continuously generates a low jitter output clock
even when all reference inputs have failed.
Frame sync support
Adaptive clocking
The AD9557 operates over an industrial temperature range of
−40°C to +85°C. If more inputs/outputs are needed, refer to the
AD9558 for the four-input/six-output version of the same part.
Optional crystal resonator for system clock input
On-chip EEPROM to store multiple power-up profiles
FUNCTIONAL BLOCK DIAGRAM
AD9557
÷3 TO ÷11
HF DIVIDER 0
CHANNEL 0
DIVIDER
REFERENCE INPUT
DIGITAL
ANALOG
PLL
AND
PLL
MONITOR MUX
÷3 TO ÷11
HF DIVIDER 1
CHANNEL 1
DIVIDER
CLOCK
MULTIPLIER
SERIAL INTERFACE
STATUS AND
CONTROL PINS
EEPROM
2
(SPI OR I C)
STABLE
SOURCE
Figure 1.
Rev. A
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved.
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