Datasheet > AD9557

AD9557

更新时间： 2022-10-09 09:26:54

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
92页	1266K
描述
Dual Input Multiservice

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AD9557 数据手册

AD9557

Data Sheet

LOGIC OUTPUTS (M3 TO M0, IRQ)

Table 5.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LOGIC OUTPUTS (M3 to M0, IRQ)

Output High Voltage (V_OH)

Output Low Voltage (V_OL)

IRQ Leakage Current

Active Low Output Mode

Active High Output Mode

DVDD3 − 0.4

I_OH= 1 mA

I_OL= 1 mA

Open-drain mode

V_OH= 3.3 V

V_OL= 0 V

0.4

−200

100

ꢀA

SYSTEM CLOCK INPUTS (XOA, XOB)

Table 6.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SYSTEM CLOCK MULTIPLIER

Output Frequency Range

750

805

MHz

The VCO range may place limitations on

nonstandard system clock input frequencies

Phase Frequency Detector (PFD) Rate

Frequency Multiplication Range

SYSTEM CLOCK REFERENCE INPUT PATH

Input Frequency Range

150

255

Assumes valid system clock and PFD rates

400

MHz

V/ꢀs

Minimum Input Slew Rate

Minimum limit imposed for jitter

performance

Common-Mode Voltage

Differential Input Voltage Sensitivity

1.05

250

1.16

1.25

Internally generated

mV p-p Minimum voltage across pins required to

ensure switching between logic states;

the instantaneous voltage on either pin

must not exceed the supply rails;

can accommodate single-ended input by

ac grounding of complementary input;

1 V p-p recommended for optimal jitter

performance

System Clock Input Doubler Duty Cycle

This is the amount of duty cycle variation

that can be tolerated on the system clock

input to use the doubler

System Clock Input = 50 MHz

System Clock Input = 20 MHz

System Clock Input = 16 MHz to 20 MHz 47

Input Capacitance

Single-ended, each pin

Input Resistance

4.2

kΩ

CRYSTAL RESONATOR PATH

Crystal Resonator Frequency Range

Maximum Crystal Motional Resistance

100

MHz

Fundamental mode, AT cut crystal

Rev. A | Page 6 of 92

1...3 4 567 8 9...92

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