Datasheet > AD9571ACPZLVD-R7

AD9571ACPZLVD-R7

更新时间： 2024-01-30 06:15:44

品牌	Logo	应用领域
亚德诺 - ADI		驱动逻辑集成电路
页数	文件大小	规格书
21页	301K
描述
Ethernet Clock Generator, 10 Clock Outputs

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AD9571ACPZLVD-R7 技术参数

Source Url Status Check Date：	2013-05-01 14:56:31.154	是否无铅：	含铅
是否Rohs认证：	符合	生命周期：	Active
零件包装代码：	QFN	包装说明：	HVQCCN,
针数：	40	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.32	系列：	CMOS
输入调节：	STANDARD	JESD-30 代码：	S-XQCC-N40
JESD-609代码：	e3	长度：	6 mm
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	湿度敏感等级：	3
功能数量：	1	反相输出次数：	10
端子数量：	40	实输出次数：	10
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	UNSPECIFIED	封装代码：	HVQCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	0.8 mm	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	6 mm	最小 fmax：	25 MHz
Base Number Matches：	1

AD9571ACPZLVD-R7 数据手册

Ethernet Clock Generator, 10 Clock Outputs

AD9571

FE ATURES

FUNCTIONAL BLOCK DIAGRAM

REFSEL

Fully integrated VCO/PLL core

0.17 ps rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz

0.41 ps rms jitter from 12 kHz to 20 MHz at 125 MHz

Input crystal or clock frequency of 25 MHz

Preset divide ratios for 156.25 MHz, 33.33 MHz,100 MHz, and

125 MHz

CMOS

XTAL

OSC

6 × 25MHz

REFCLK

PFD/CP

Choice of LVPECL or LVDS output format

Integrated loop filter

3RD-ORDER

LPF

6 copies of reference clock output

Rates configured via strapping pins

Space saving 6 mm × 6 mm 40-lead LFCSP

0.48 W power dissipation (LVDS operation)

0.69 W power dissipation (LVPECL operation)

3.3 V operation

LVPECL OR

LVDS

VCO

1 × 156.25MHz

2 × 100MHz OR

125MHz

APPLICATIONS

CMOS

Ethernet line cards, switches, and routers

SCSI, SATA, and PCI-express

1 × 33.33MHz

FORCE_LOW

PCI support included

AD9571

Low jitter, low phase noise clock generation

FREQSEL

Figure 1.

GENERAL DESCRIPTION

feedback divider and output divider. By connecting an external

crystal or reference clock to the REFCLK pin, frequencies up to

156.25 MHz can be locked to the input reference.

The AD9571 provides a multioutput clock generator function

comprising a dedicated PLL core that is optimized for Ethernet

line card applications. The integer-N PLL design is based on the

Analog Devices, Inc., proven portfolio of high performance, low

jitter frequency synthesizers to maximize network performance.

Other applications with demanding phase noise and jitter

requirements also benefit from this part.

Each output divider and feedback divider ratio is prepro-

grammed for the required output rates. No external loop filter

components are required, thus conserving valuable design time

and board space.

The PLL section consists of a low noise phase frequency

detector (PFD), a precision charge pump (CP), a low phase

noise voltage controlled oscillator (VCO), and a preprogrammed

The AD9571 is available in a 40-lead 6 mm × 6 mm lead frame

chip scale package and can be operated from a single 3.3 V

supply. The operating temperature range is −40°C to +85°C.

OPTIONAL

CX-4 PHY

CPU

ISLAND

XAUI

6 × 25MHz

2 × 125MHz

48 + 2 SWITCH/MAC

AD9571

1 × 156.25MHz

1 × 33.33MHz

2 × OCTAL 2 × OCTAL 2 × OCTAL 2 × OCTAL

GbE PHY GbE PHY GbE PHY GbE PHY

Figure 2. Typical Application

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibilityisassumedbyAnalog Devices for its use, norforany infringements ofpatents or other

rightsofthirdpartiesthat mayresult fromitsuse.Specificationssubjectto changewithoutnotice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarksandregisteredtrademarksarethepropertyoftheirrespective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

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