Data Sheet
AD9557
REFERENCE INPUTS
Table 7.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DIFFERENTIAL OPERATION
Frequency Range
Sinusoidal Input
LVPECL Input
10
0.002
750
1250
MHz
MHz
The reference input divide-by-2 block must be engaged
for fIN > 705 MHz
LVDS Input
0.002
40
750
MHz
V/ꢀs
The reference input divide-by-2 block must be engaged
for fIN > 705 MHz
Minimum limit imposed for jitter performance
Minimum Input Slew Rate
Common-Mode Input Voltage
AC-Coupled
1.9
1.0
2
2.1
2.4
V
V
Internally generated
DC-Coupled
Differential Input Voltage Sensitivity
mV
Minimum differential voltage across pins is required to
ensure switching between logic levels; instantaneous
voltage on either pin must not exceed the supply rails
fIN < 800 MHz
240
320
400
mV
mV
mV
mV
kΩ
fIN = 800 to 1050 MHz
fIN = 1050 to 1250 MHz
Differential Input Voltage Hysteresis
Input Resistance
58
21
3
100
Input Capacitance
pF
Minimum Pulse Width High
LVPECL
LVDS
390
640
ps
ps
Minimum Pulse Width Low
LVPECL
LVDS
390
640
ps
ps
SINGLE-ENDED OPERATION
Frequency Range (CMOS)
Minimum Input Slew Rate
Input Voltage High (VIH)
1.2 V to 1.5 V Threshold Setting
1.8 V to 2.5 V Threshold Setting
3.0 V to 3.3 V Threshold Setting
Input Voltage Low (VIL)
1.2 V to 1.5 V Threshold Setting
1.8 V to 2.5 V Threshold Setting
3.0 V to 3.3 V Threshold Setting
Input Resistance
0.002
40
300
MHz
V/ꢀs
Minimum limit imposed for jitter performance
1.0
1.4
2.0
V
V
V
0.35
0.5
1.0
V
V
V
kΩ
pF
ns
ns
47
3
Input Capacitance
Minimum Pulse Width High
Minimum Pulse Width Low
1.5
1.5
Rev. A | Page 7 of 92