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AD9557

更新时间: 2022-10-09 09:26:54
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
92页 1266K
描述
Dual Input Multiservice

AD9557 数据手册

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Data Sheet  
AD9557  
POWER DISSIPATION  
Table 3.  
Parameter  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
POWER DISSIPATION  
Typical Configuration  
0.36  
0.55  
0.76  
W
System clock: 49.152 MHz crystal; DPLL active;  
both 19.44 MHz input references in differential mode;  
one HSTL driver at 644.53125 MHz;  
one 3.3 V CMOS driver at 161.1328125 MHz and 80 pF  
capacitive load on CMOS output  
All Blocks Running  
0.39  
0.61  
44  
0.85  
125  
W
System clock: 49.152 MHz crystal; DPLL active;  
both input references in differential mode;  
one HSTL driver at 750 MHz;  
two 3.3 V CMOS drivers at 250 MHz and 80 pF capacitive  
load on CMOS outputs  
Full Power-Down  
mW  
Typical configuration with no external pull-up or pull-  
down resistors; about 2/3 of this power is on AVDD3  
Incremental Power Dissipation  
Conditions = typical configuration; table values show the  
change in power due to the indicated operation  
Input Reference On/Off  
Differential Without Divide-by-2  
Differential With Divide-by-2  
Single-Ended Without Divide-by-2  
Output Distribution Driver On/Off  
LVDS (at 750 MHz)  
20  
26  
5
25  
32  
7
32  
40  
9
mW  
mW  
mW  
Additional current draw is in the DVDD3 domain only  
Additional current draw is in the DVDD3 domain only  
Additional current draw is in the DVDD3 domain only  
12  
14  
14  
18  
17  
21  
21  
27  
22  
28  
28  
36  
mW  
mW  
mW  
mW  
Additional current draw is in the AVDD domain only  
Additional current draw is in the AVDD domain only  
A single 1.8 V CMOS output with an 80 pF load  
A single 3.3 V CMOS output with an 80 pF load  
HSTL (at 750 MHz)  
1.8 V CMOS (at 250 MHz)  
3.3 V CMOS (at 250 MHz)  
Other Blocks On/Off  
Second RF Divider  
Channel Divider Bypassed  
36  
10  
51  
17  
64  
23  
mW  
mW  
Additional current draw is in the AVDD domain only  
Additional current draw is in the AVDD domain only  
LOGIC INPUTS (RESET, SYNC, PINCONTROL, M3 TO M0)  
Table 4.  
Parameter  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
LOGIC INPUTS (RESET, SYNC, PINCONTROL)  
Input High Voltage (VIH)  
Input Low Voltage (VIL)  
Input Current (IINH, IINL)  
Input Capacitance (CIN)  
LOGIC INPUTS (M3 to M0)  
Input High Voltage (VIH)  
Input ½ Level Voltage (VIM)  
Input Low Voltage (VIL)  
Input Current (IINH, IINL)  
Input Capacitance (CIN)  
2.1  
V
V
μA  
pF  
0.8  
100  
50  
3
2.5  
1.0  
V
V
V
μA  
pF  
2.2  
0.6  
100  
60  
3
Rev. A | Page 5 of 92  
 
 

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