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AD9548 PDF预览

AD9548

更新时间: 2024-02-23 03:17:31
品牌 Logo 应用领域
亚德诺 - ADI 时钟发生器
页数 文件大小 规格书
112页 1935K
描述
Quad/Octal Input Network Clock Generator/Synchronizer

AD9548 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN,针数:88
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:1.64
JESD-30 代码:S-XQCC-N88JESD-609代码:e3
长度:12 mm湿度敏感等级:3
端子数量:88最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
主时钟/晶体标称频率:1000 MHz认证状态:Not Qualified
座面最大高度:0.9 mm最大供电电压:1.89 V
最小供电电压:1.71 V标称供电电压:1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:12 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

AD9548 数据手册

 浏览型号AD9548的Datasheet PDF文件第4页浏览型号AD9548的Datasheet PDF文件第5页浏览型号AD9548的Datasheet PDF文件第6页浏览型号AD9548的Datasheet PDF文件第8页浏览型号AD9548的Datasheet PDF文件第9页浏览型号AD9548的Datasheet PDF文件第10页 
AD9548  
REFERENCE INPUTS (REFA/REFAA TO REFD/REFDD)  
Table 8.  
Parameter  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
DIFFERENTIAL OPERATION  
Frequency Range  
Sinusoidal Input  
LVPECL Input  
10  
1
1
750  
750 × 106  
750 × 106  
MHz  
Hz  
Hz  
LVDS Input  
Minimum Input Slew Rate  
40  
V/ꢀs  
Minimum limit imposed for jitter  
performance  
Common-Mode Input Voltage  
2
V
Internally generated  
Differential Input Voltage Sensitivity  
65  
mV  
Minimum differential voltage across  
pins required to ensure switching  
between logic levels; the  
instantaneous voltage on either pin  
must not exceed the supply rails  
Input Resistance  
Input Capacitance  
25  
3
kΩ  
pF  
Minimum Pulse Width High  
Minimum Pulse Width Low  
SINGLE-ENDED OPERATION  
Frequency Range (CMOS)  
Minimum Input Slew Rate  
620  
620  
ps  
ps  
1
40  
250 ×106  
Hz  
V/ꢀs  
Minimum limit imposed for jitter  
performance  
Input Voltage High (VIH)  
1.2 V to 1.5 V Threshold Setting  
1.8 V to 2.5 V Threshold Setting  
3.0 V to 3.3 V Threshold Setting  
Input Voltage Low (VIL)  
0.9  
1.2  
1.9  
V
V
V
1.2 V to 1.5 V Threshold Setting  
1.8 V to 2.5 V Threshold Setting  
3.0 V to 3.3 V Threshold Setting  
Input Resistance  
Input Capacitance  
Minimum Pulse Width High  
Minimum Pulse Width Low  
0.27  
0.5  
1.0  
V
V
V
kΩ  
pF  
ns  
ns  
45  
3
1.5  
1.5  
REFERENCE MONITORS  
Table 9.  
Parameter  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
REFERENCE MONITORS  
Reference Monitor  
Loss of Reference Detection  
Time  
1.2  
sec  
Calculated using the nominal phase detector period  
1
(NPDP = R/fREF  
)
Frequency Out-of Range Limits 9.54 × 10−7  
0.1  
65.535  
65.535  
Δf/fREF  
sec  
sec  
Programmable (lower bound subject to quality of SYSCLK)  
Programmable in 1 ms increments  
Programmable in 1 ms increments  
Validation Timer  
Redetect Timer  
0.001  
0.001  
1 fREF is the frequency of the active reference; R is the frequency division factor determined by the R-divider.  
Rev. 0 | Page 7 of 112  
 
 

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