Datasheet > AD9549APCBZ

AD9549APCBZ

更新时间： 2024-09-18 12:47:47

品牌	Logo	应用领域
亚德诺 - ADI		时钟发生器
页数	文件大小	规格书
76页	1905K
描述
Dual Input Network Clock Generator/Synchronizer

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AD9549APCBZ 数据手册

Dual Input Network Clock

Generator/Synchronizer

AD9549

FEATURES

APPLICATIONS

Flexible reference inputs

Network synchronization

Input frequencies: 8 kHz to 750 MHz

Two reference inputs

Loss of reference indicators

Reference clock jitter cleanup

SONET/SDH clocks up to OC-192, including FEC

Stratum 3/3E reference clocks

Wireless base station, controllers

Cable infrastructure

Auto and manual holdover modes

Auto and manual switchover modes

Smooth A-to-B phase transition on outputs

Excellent stability in holdover mode

Programmable 16 + 1-bit input divider, R

Differential HSTL clock output

Data communications

GENERAL DESCRIPTION

The AD9549 provides synchronization for many systems,

including synchronous optical networks (SONET/SDH). The

AD9549 generates an output clock, synchronized to one of two

external input references. The external references may contain

significant time jitter, also specified as phase noise. Using a

digitally controlled loop and holdover circuitry, the AD9549

continues to generate a clean (low jitter), valid output clock during

a loss of reference condition, even when both references have failed.

Output frequencies to 750 MHz

Low jitter clock doubler for frequencies of >400 MHz

Single-ended CMOS output for frequencies of <150 MHz

Programmable digital loop filter (<1 Hz to ~100 kHz)

High speed digitally controlled oscillator (DCO) core

Direct digital synthesizer (DDS) with integrated 14-bit DAC

Excellent dynamic performance

Programmable 16 + 1-bit feedback divider, S

Software controlled power-down

Available 64-lead LFCSP package

The AD9549 operates over an industrial temperature range of

−40°C to +85°C.

BASIC BLOCK DIAGRAM

AD9549

S1 TO S4

FDBK_IN

FILTER

DAC_OUT

REFERENCE

MONITORS

AND

REFA_IN

REFB_IN

OUT

DIGITAL PLL

R, S DIVIDERS

HOLDOVER

CLOCK

OUTPUT

DRIVERS

OUT_CMOS

SWITCHING

SERIAL PORT,

I/O LOGIC

SYSTEM CLOCK

MULTIPLIER

DIGITAL INTERFACE

Figure 1.

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rightsof third parties that may result fromits use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

12 3 4 5 6 7...76

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与AD9549APCBZ相关器件

型号	品牌	获取价格	描述	数据表
AD9549BCPZ	ADI	获取价格	Dual Input Network Clock Generator/Synchronizer
AD9549BCPZ-REEL7	ADI	获取价格	IC 750 MHz, OTHER CLOCK GENERATOR, QCC64, 9 X 9 MM, ROHS COMPLIANT, MO-220VMMD, LFCSP-64,
AD9549XCPZ	ADI	获取价格	Dual Input Network Clock Generator/Synchronizer
AD9550	ADI	获取价格	Integer-N Clock Translator for Wireline Communications
AD9550/PCBZ	ADI	获取价格	Integer-N Clock Translator for Wireline Communications
AD9550BCPZ	ADI	获取价格	Integer-N Clock Translator for Wireline Communications
AD9550BCPZ-REEL7	ADI	获取价格	Integer-N Clock Translator for Wireline Communications
AD9551	ADI	获取价格	Multiservice Clock Generator
AD9551/PCBZ	ADI	获取价格	Multiservice Clock Generator
AD9551BCPZ	ADI	获取价格	Multiservice Clock Generator

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