#
$65<)343
®
89#45;.ð;#&026#)ODVK#((3520
)HDWXUHV
• Organization: 128K × 8 bits
• Sector Erase architecture
• JEDEC standard write cycle commands
- protects data from accidental changes
• Program/ erase cycle end signals:
- Four 32K × 8 sectors
• Single 5.0±0.5V power supply for read/ write operations
• High speed 120/ 150 ns address access time
• Low power consumption:
- 30 mA maximum read current
- 50 mA maximum program current
- 1.5 mA maximum standby current
- 1 mA maximum standby current (low power)
• 10,000 write/ erase cycle endurance
- Data polling
- DQ6 toggle
• Low V write lock-out below 3.2V
CC
• JEDEC standard packages and pinouts:
- 32-pin DIP
- 32-pin PLCC
- 32-pin TSOP
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3LQ#DUUDQJHPHQW
DQ ~DQ
0
7
32-pin
PDIP
32-pin
PLCC
V
CC
V
SS
Erase voltage
switch
Input/output
buffers
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
WE
NC*
A14
A13
A8
A9
A11
OE
State
WE
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
5
6
7
8
29
28
27
26
25
24
23
22
21
A14
A13
A8
A9
A11
OE
A10
CE
DQ7
control
Command
register
Program voltage
switch
AS29F010
9
9
10
11
12
13
14
15
16
A10
CE
10
11
12
13
Data
latch
DQ7
DQ6
DQ5
DQ4
DQ3
Chip enable
Output enable
Logic
CE
OE
V
SS
32-pin
TSOP
Program/erase
pulse timer
Low V detector
Y-Decoder
X-Decoder
Y-Gating
CC
A11
A9
1
2
3
4
5
6
7
8
9
OE
32
31
30
29
28
27
26
25
24
23
22
21
20
19
A10
CE
A ~A
0
16
1,048,576 bit
Cell matrix
A8
A13
A14
NC
WE
DQ7
DQ6
DQ5
DQ4
DQ3
V
CC
AS29F010
V
NC
A16
A15
A12
A7
SS
10
DQ2
DQ1
DQ0
A0
11
12
13
14
15
16
A6
A1
A5
18
A2
A4
17
A3
6HOHFWLRQ#JXLGH
AS29F010-120
AS29F010-150
Unit
ns
Maximum access time
Chip enable access time
Output enable access time
tAA
tCE
tOE
120
120
50
150
150
50
ns
ns
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Copyright ©1998 Alliance Semiconductor. All rights reserved.