Datasheet > 935319923518

935319923518

更新时间： 2024-09-20 19:56:47

品牌	Logo	应用领域
恩智浦 - NXP		时钟微控制器外围集成电路
页数	文件大小	规格书
136页	1511K
描述
Microcontroller

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935319923518 技术参数

生命周期：	Active	包装说明：	LFBGA,
Reach Compliance Code：	unknown	风险等级：	5.65
具有ADC：	YES	地址总线宽度：	32
位大小：	32	最大时钟频率：	40 MHz
DMA 通道：	YES	外部数据总线宽度：	64
长度：	14 mm	端子数量：	257
PWM 通道：	YES	封装代码：	LFBGA
封装形状：	SQUARE	封装形式：	GRID ARRAY, LOW PROFILE, FINE PITCH
速度：	120 MHz	最大供电电压：	3.63 V
最小供电电压：	3 V	标称供电电压：	3.3 V
表面贴装：	YES	端子形式：	BALL
端子节距：	0.5 mm	端子位置：	BOTTOM
宽度：	14 mm	uPs/uCs/外围集成电路类型：	MICROCONTROLLER RISC
Base Number Matches：	1

935319923518 数据手册

Freescale Semiconductor

Data Sheet: Advance Information

Document Number: MPC5643L

Rev. 9, 6/2013

MPC5643L

MAPBGA–225

QFN12

15 mm x 15 mm

##_mm_x_##mm

SOT-343R

##_mm_x_##mm

144 LQFP

PKG-TBD

Qorivva MPC5643L

Microcontroller Data Sheet

## mm x ## mm

TBD

257 MAPBGA

(20 x 20 x 1.4 mm)

(14 x 14 x 0.8 mm)

—

Cyclic redundancy check (CRC) unit

•

High-performance e200z4d dual core

•

Decoupled Parallel mode for high-performance use of

replicated cores

Nexus Class 3+ interface

Interrupts

—

GPIOs individually programmable as input, output or

special function

Three 6-channel general-purpose eTimer units

2 FlexPWM units

—

32-bit Power Architecture^®technology CPU

Core frequency as high as 120 MHz

Dual issue five-stage pipeline core

Variable Length Encoding (VLE)

Memory Management Unit (MMU)

4 KB instruction cache with error detection code

Signal processing engine (SPE)

•

Replicated 16-priority controller

Replicated 16-channel eDMA controller

•

Memory available

•

—

1 MB flash memory with ECC

128 KB on-chip SRAM with ECC

Built-in RWW capabilities for EEPROM emulation

—

Four 16-bit channels per module

•

Communications interfaces

—

SIL3/ASILD innovative safety concept: LockStep mode and

Fail-safe protection

2 LINFlexD channels

3 DSPI channels with automatic chip select

generation

2 FlexCAN interfaces (2.0B Active) with 32

message objects

FlexRay module (V2.1 Rev. A) with 2 channels,

64 message buffers and data rates up to 10 Mbit/s

—

Sphere of replication (SoR) for key components (such as

CPU core, eDMA, crossbar switch)

—

Fault collection and control unit (FCCU)

Redundancy control and checker unit (RCCU) on outputs

of the SoR connected to FCCU

—

Boot-time Built-In Self-Test for Memory (MBIST) and

Logic (LBIST) triggered by hardware

Boot-time Built-In Self-Test for ADC and flash memory

triggered by software

•

Two 12-bit analog-to-digital converters (ADCs)

—

16 input channels

Programmable cross triggering unit (CTU) to

synchronize ADCs conversion with timer and

PWM

—

Replicated safety enhanced watchdog

Replicated junction temperature sensor

Non-maskable interrupt (NMI)

16-region memory protection unit (MPU)

Clock monitoring units (CMU)

•

Sine wave generator (D/A with low pass filter)

On-chip CAN/UART bootstrap loader

Single 3.0 V to 3.6 V voltage supply

•

Ambient temperature range –40 °C to 125 °C

Junction temperature range –40 °C to 150 °C

Power management unit (PMU)

This document contains information on a product under development. Freescale reserves

the right to change or discontinue this product without notice.

12 3 4 5 6 7...136

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