Datasheet > 935320492557

935320492557

更新时间： 2024-11-10 21:20:15

品牌	Logo	应用领域
恩智浦 - NXP		开关
页数	文件大小	规格书
29页	1072K
描述
Switching Regulator

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935320492557 技术参数

生命周期：	Active	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.74
模拟集成电路 - 其他类型：	SWITCHING REGULATOR	Base Number Matches：	1

935320492557 数据手册

Document Number: MC34712

Rev. 8.0, 8/2016

NXP Semiconductors

Data Sheet: Technical Data

3.0 A 1.0 MHz fully integrated DDR

switch-mode power supply

34712

The SMARTMOS 34712 is a highly integrated, space efficient, low cost, single

synchronous buck switching regulator with integrated N-channel power

MOSFETs. It is a high performance point-of-load (PoL) power supply with the

ability to track an external reference voltage.

SWITCH-MODE POWER SUPPLY

Its high efficient 3.0 A sink and source capability combined with its voltage

tracking/sequencing ability and tight output regulation, makes it ideal to provide

the termination voltage (V_TT) for modern data buses such as Double-Data-Rate

(DDR) memory buses, including but not limited to DDR, DDR2, DDR3, and

DDR4 memories. It also provides a buffered output reference voltage (V_REF) to

the memory chipset

The 34712 offers the designer the flexibility of many control, supervisory, and

protection functions to allow for easy implementation of complex designs. It is

housed in a Pb-free, thermally enhanced, and space efficient 24 pin exposed

pad QFN.

Features

• 50 mΩ integrated N-channel power MOSFETs

• Input voltage operating range from 3.0 V to 6.0 V

EP SUFFIX

98ARL10577D

24-PIN QFN

•

1% Accurate output voltage, ranging from 0.6 V to 1.35 V

1% Accurate buffered reference output voltage

• Programmable switching frequency range from 200 kHz to 1.0 MHz with a

default of 1.0 MHz

• Overcurrent limit and short-circuit protection

• Thermal shutdown

• Output overvoltage and undervoltage detection

• Active low power-good output signal

• Active low standby and shutdown inputs

V_IN

(3.0 TO 6.0 V)

34712

PVIN

BOOT

TERMINATING

RESISTORS

V_DDQ

VREFIN

V_TT

VOUT

VIN

MEMORY

BUS

V_DDQ

VDDI

FREQ

GND

INV

DDR MEMORY

CHIPSET

COMP

V_DDQ

VREFOUT

V_REF

V_IN

DDR MEMORY

CONTROLLER

PGND

MCU

STBY

Figure 1. 34712 simplified application diagram

12 3 4 5 6 7...29

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