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89HPES24NT3ZBBX8 PDF预览

89HPES24NT3ZBBX8

更新时间： 2024-01-16 04:57:22
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
31页 462K
描述
Bus Controller, PBGA420

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89HPES24NT3ZBBX8 技术参数

是否Rohs认证： 不符合生命周期：Active
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.82
JESD-30 代码：S-PBGA-B420JESD-609代码：e0
湿度敏感等级：3端子数量：420
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA420,26X26,40封装形状：SQUARE
封装形式：GRID ARRAY电源：1,3.3 V
认证状态：Not Qualified子类别：Bus Controllers
表面贴装：YES温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn63Pb37)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
Base Number Matches：1

89HPES24NT3ZBBX8 数据手册

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89HPES24NT3  
Data Sheet  
24-Lane 3-Port Non-Transparent  
PCI Express® Switch  
®
◆
Flexible Architecture with Numerous Configuration Options  
Device Overview  
–
–
Port arbitration schemes utilizing round robin  
Supports automatic per port link width negotiation (x8, x4, x2,  
or x1)  
The 89HPES24NT3 is a member of the IDT PRECISE™ family of  
PCI Express® switching solutions offering the next-generation I/O inter-  
connect standard. The PES24NT3 is a 24-lane, 3-port peripheral chip  
that performs PCI Express Base switching with a feature set optimized  
for high performance applications such as servers, storage, and commu-  
nications/networking. It provides high-performance switching functions  
between a PCIe® upstream port, a transparent downstream port, and a  
non-transparent downstream port.  
–
–
–
Static lane reversal on all ports  
Automatic polarity inversion on all lanes  
Supports locked transactions, allowing use with legacy soft-  
ware  
–
–
Ability to load device configuration from serial EEPROM  
Ability to control device via SMBus  
◆
Non-Transparent Port  
With non-transparent bridging (NTB) functionality, the PES24NT3  
can be used standalone or as a chipset with IDT PCIe System Intercon-  
nect Switches in multi-host and intelligent I/O applications such as  
communications, storage, and blade servers where inter-domain  
communication is required.  
–
–
Crosslink support on NTB port  
Four mapping windows supported  
• Each may be configured as a 32-bit memory or I/O window  
• May be paired to form a 64-bit memory window  
Interprocessor communication  
–
• Thirty-two inbound and outbound doorbells  
• Four inbound and outbound message registers  
• Two shared scratchpad registers  
Allows up to sixteen masters to communicate through the non-  
transparent port  
No limit on the number of supported outstanding transactions  
through the non-transparent bridge  
Completely symmetric non-transparent bridge operation  
allows similar/same configuration software to be run  
Supports direct connection to a transparent or non-transparent  
port of another switch  
Features  
◆
High Performance PCI Express Switch  
–
–
–
–
–
–
–
–
–
–
Twenty-four PCI Express lanes (2.5Gbps), three switch ports  
Delivers 96 Gbps (12 GBps) of aggregate switching capacity  
Low latency cut-through switch architecture  
Support for Max Payload size up to 2048 bytes  
Supports one virtual channel and eight traffic classes  
PCI Express Base specification Revision 1.0a compliant  
Block Diagram  
3-Port Switch Core  
Port  
Arbitration  
Frame Buffer  
Route Table  
Scheduler  
Transaction Layer  
Transaction Layer  
Data Link Layer  
Transaction Layer  
Data Link Layer  
Non-  
Transparent  
Bridge  
Data Link Layer  
Multiplexer / Demultiplexer  
Multiplexer / Demultiplexer  
Multiplexer / Demultiplexer  
Phy  
Phy  
Phy  
Phy  
Phy  
Phy  
Phy  
Phy  
Phy  
Logical  
Layer  
Logical  
Layer  
Logical  
Layer  
Logical  
Layer  
Logical  
Layer  
Logical  
Layer  
Logical  
Layer  
Logical  
Layer  
Logical  
Layer  
...  
...  
...  
SerDes SerDes  
SerDes  
SerDes SerDes  
SerDes  
SerDes SerDes  
SerDes  
24 PCI Express Lanes  
x8 Upstream Port and Two x8 Downstream Ports  
Figure 1 Internal Block Diagram  
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.  
1 of 31  
January 5, 2009  
DSC 6925  
© 2009 Integrated Device Technology, Inc.  
1234567...31

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