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89HPES24T3G2ZCBL PDF预览

89HPES24T3G2ZCBL

更新时间： 2024-09-25 15:42:03
品牌 Logo 应用领域
艾迪悌 - IDT 时钟PC外围集成电路
页数 文件大小 规格书
48页 1036K
描述
PCI Bus Controller, PBGA676, 27 X 27 MM, 1 MM PITCH, FCBGA-676

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89HPES24T3G2ZCBL 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：BGA
包装说明：FCBGA-676针数：676
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.08
其他特性：ALSO REQUIRES 3.3V SUPPLY地址总线宽度：
总线兼容性：PCI最大时钟频率：125 MHz
外部数据总线宽度：JESD-30 代码：S-PBGA-B676
JESD-609代码：e0长度：27 mm
端子数量：676最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA676,26X26,40
封装形状：SQUARE封装形式：GRID ARRAY
峰值回流温度（摄氏度）：225电源：1,2.5,3.3 V
认证状态：Not Qualified座面最大高度：3.22 mm
子类别：Bus Controllers最大供电电压：1.1 V
最小供电电压：0.9 V标称供电电压：1 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
宽度：27 mmuPs/uCs/外围集成电路类型：BUS CONTROLLER, PCI
Base Number Matches：1

89HPES24T3G2ZCBL 数据手册

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89HPES24T3G2  
Data Sheet  
24-Lane 3-Port  
Gen2 PCI Express® Switch  
®
–
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Dynamic link width reconfiguration for power/performance  
optimization  
Configurable downstream port PCI-to-PCI bridge device  
numbering  
Device Overview  
The 89HPES24T3G2 is a member of IDT’s PRECISE™ family of PCI  
Express® switching solutions. The PES24T3G2 is a 24-lane, 3-port  
Gen2 peripheral chip that performs PCI Express base switching with a  
feature set optimized for high performance applications such as servers,  
storage, and communications systems. It provides connectivity and  
switching functions between a PCI Express upstream port and two  
downstream ports and supports switching between downstream ports.  
–
–
Crosslink support  
Supports ARI forwarding defined in the Alternative Routing-ID  
Interpretation (ARI) ECN for virtualized and non-virtualized  
environments  
–
Ability to load device configuration from serial EEPROM  
◆
◆
Legacy Support  
Features  
◆
–
PCI compatible INTx emulation  
High Performance PCI Express Switch  
–
Supports bus locked transactions, allowing use of PCI Express  
with legacy software  
–
Twenty-four 5 Gbps Gen2 PCI Express lanes supporting  
5 Gbps and 2.5 Gbps operation  
Highly Integrated Solution  
–
–
–
–
Up to three switch ports  
Support for Max Payload Size up to 2048 bytes  
Supports one virtual channel and eight traffic classes  
Fully compliant with PCI Express base specification Revision  
2.0  
–
Requires no external components  
–
Incorporates on-chip internal memory for packet buffering and  
queueing  
–
Integrates twenty-four 5 Gbps / 2.5 Gbps embedded SerDes,  
8B/10B encoder/decoder (no separate transceivers needed)  
◆
Flexible Architecture with Numerous Configuration Options  
◆
Reliability, Availability, and Serviceability (RAS) Features  
–
–
–
–
–
Automatic per port link width negotiation to x8, x4, x2, or x1  
Automatic lane reversal on all ports  
Automatic polarity inversion  
Supports in-band hot-plug presence detect capability  
Supports external signal for hot plug event notification allowing  
SCI/SMI generation for legacy operating systems  
–
–
–
Ability to disable peer-to-peer communications  
Supports ECRC and Advanced Error Reporting  
All internal data and control RAMs are SECDED ECC  
protected  
–
–
Supports PCI Express hot-plug on all downstream ports  
Supports upstream port hot-plug  
Block Diagram  
3-Port Switch Core / 24 Gen2 PCI Express Lanes  
Port  
Frame Buffer  
Route Table  
Arbitration  
Scheduler  
Transaction Layer  
Transaction Layer  
Data Link Layer  
Transaction Layer  
Data Link Layer  
Data Link Layer  
Multiplexer / Demultiplexer  
Multiplexer / Demultiplexer  
Multiplexer / Demultiplexer  
Phy  
Phy  
Phy  
Phy  
Phy  
Phy  
Phy  
Phy  
Phy  
Logical  
Layer  
Logical  
Layer  
Logical  
Layer  
Logical  
Layer  
Logical  
Layer  
Logical  
Layer  
Logical  
Layer  
Logical  
Layer  
Logical  
Layer  
...  
...  
...  
SerDes SerDes  
SerDes  
SerDes SerDes  
SerDes  
SerDes SerDes  
SerDes  
Figure 1 Internal Block Diagram  
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.  
1 of 48  
September 29, 2010  
DSC 6930  
© 2010 Integrated Device Technology, Inc.  
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