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89HPES32H8ZAARI

更新时间: 2024-09-25 03:11:11
品牌 Logo 应用领域
艾迪悌 - IDT PC
页数 文件大小 规格书
40页 878K
描述
32-Lane 8-Port PCI Express System Interconnect Switch

89HPES32H8ZAARI 数据手册

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89HPES32H8  
Data Sheet  
32-Lane 8-Port PCI Express®  
System Interconnect Switch  
®
Flexible Architecture with Numerous Configuration Options  
Device Overview  
Port arbitration schemes utilizing round robin algorithms  
Virtual channels arbitration based on priority  
Automatic per port link width negotiation to x8, x4, x2 or x1  
Automatic lane reversal on all ports  
Automatic polarity inversion on all ports  
Supports locked transactions, allowing use with legacy soft-  
ware  
The 89HPES32H8 is a member of the IDT PRECISE™ family of PCI  
Express® switching solutions. The PES32H8 is a 32-lane, 8-port system  
interconnect switch optimized for PCI Express packet switching in high-  
performance applications, supporting multiple simultaneous peer-to-  
peer traffic flows. Target applications include servers, storage, communi-  
cations, and embedded systems.  
Features  
Ability to load device configuration from serial EEPROM  
Ability to control device via SMBus  
High Performance PCI Express Switch  
Eight maximum switch ports  
Highly Integrated Solution  
Four main ports each of which consists of eight SerDes  
Each x8 main port can further bifurcate to 2 x4-ports  
Thirty-two 2.5 Gbps embedded SerDes  
Requires no external components  
Incorporates on-chip internal memory for packet buffering and  
queueing  
Supports pre-emphasis and receive equalization on per-port  
basis  
Integrates thirty-two 2.5 Gbps embedded full duplex SerDes,  
8B/10B encoder/decoder (no separate transceivers needed)  
Delivers 128 Gbps (16 GBps) aggregate switching capacity  
Low-latency cut-through switch architecture  
Support for Max Payload Size up to 2048 bytes  
Supports two virtual channels and eight traffic classes  
PCI Express Base Specification Revision 1.1 compliant  
Reliability, Availability, and Serviceability (RAS) Features  
Redundant upstream port failover capability  
Internal end-to-end parity protection on all TLPs ensures data  
integrity even in systems that do not implement end-to-end  
CRC (ECRC)  
Block Diagram  
x8/x4/x2/x1  
x8/x4/x2/x1  
SerDes  
SerDes  
DL/Transaction Layer  
DL/Transaction Layer  
Port  
Arbitration  
Route Table  
Frame Buffer  
8-Port Switch Core  
Scheduler  
DL/Transaction Layer  
SerDes  
DL/Transaction Layer  
SerDes  
x8/x4/x2/x1  
x8/x4/x2/x1  
Figure 1 Internal Block Diagram  
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.  
1 of 40  
July 19, 2007  
© 2007 Integrated Device Technology, Inc.  

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