89HPES48T12
Data Sheet
48-Lane 12-Port
PCI Express® Switch
®
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Supports one virtual channel and eight traffic classes
PCI Express Base Specification Revision 1.1 compliant
Device Overview
The 89HPES48T12 is a member of the IDT PRECISE™ family of
PCI Express® switching solutions. The PES48T12 is a 48-lane, 12-port
peripheral chip that performs PCI Express packet switching with a
feature set optimized for high-performance applications such as servers,
storage, and communications/networking. It provides connectivity and
switching functions between a PCI Express upstream port and up to
eleven downstream ports and supports switching between downstream
ports.
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Flexible Architecture with Numerous Configuration Options
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Port arbitration schemes utilizing round robin algorithms
Automatic per port link width negotiation to x8, x4, x2 or x1
Automatic lane reversal on all ports
Automatic polarity inversion on all lanes
Supports locked transactions, allowing use with legacy soft-
ware
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Ability to load device configuration from serial EEPROM
Ability to control device via SMBus
Features
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High Performance PCI Express Switch
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Highly Integrated Solution
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Twelve switch ports
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Requires no external components
Incorporates on-chip internal memory for packet buffering and
queueing
Integrates forty-eight 2.5 Gbps embedded full duplex SerDes,
8B/10B encoder/decoder (no separate transceivers needed)
• Six main ports each of which consists of 8 SerDes
• Each x8 main port can further bifurcate to 2 x4-ports
Forty-eight 2.5 Gbps embedded SerDes
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• Supports pre-emphasis and receive equalization on per-port
basis
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Reliability, Availability, and Serviceability (RAS) Features
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Delivers 192 Gbps (24 GBps) of aggregate switching capacity
Low-latency cut-through switch architecture
Support for Max Payload Size up to 2048 bytes
Redundant upstream port failover capability
Supports optional PCI Express end-to-end CRC checking
Block Diagram
x8/x4/x2/x1
SerDes
DL/Transaction Layer
Upstream
Port
Arbitration
Route Table
Frame Buffer
12-Port Switch Core
Scheduler
DL/Transaction Layer
DL/Transaction Layer
SerDes
DL/Transaction Layer
SerDes
DL/Transaction Layer
SerDes
DL/Transaction Layer
SerDes
SerDes
x8/x4/x2/x1
x8/x4/x2/x1
x8/x4/x2/x1
x8/x4/x2/x1
x8/x4/x2/x1
48 PCI Express Lanes
Up to 6 x8 ports or 12 x4 Ports
Figure 1 Internal Block Diagram
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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July 19, 2007
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© 2007 Integrated Device Technology, Inc.