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89HPES4T4ZBNQ PDF预览

89HPES4T4ZBNQ

更新时间: 2024-09-26 13:05:03
品牌 Logo 应用领域
艾迪悌 - IDT PC
页数 文件大小 规格书
23页 402K
描述
PCI Bus Controller, 10 X 10 MM, 0.65 MM PITCH, QFN-132

89HPES4T4ZBNQ 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Active零件包装代码:QFN
包装说明:QFN-132针数:132
Reach Compliance Code:compliantECCN代码:3A001.A.3
HTS代码:8542.31.00.01风险等级:5.15
Is Samacsys:N地址总线宽度:
总线兼容性:PCI最大时钟频率:125 MHz
外部数据总线宽度:JESD-30 代码:S-XQCC-N132
JESD-609代码:e0长度:10 mm
端子数量:132最高工作温度:70 °C
最低工作温度:封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装等效代码:LGA132,20X20,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):225电源:1,3.3 V
认证状态:Not Qualified座面最大高度:0.9 mm
子类别:Bus Controllers最大供电电压:1.1 V
最小供电电压:0.9 V标称供电电压:1 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:NO LEAD端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:10 mmuPs/uCs/外围集成电路类型:BUS CONTROLLER, PCI
Base Number Matches:1

89HPES4T4ZBNQ 数据手册

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89HPES4T4  
Data Sheet  
Advance Information*  
4-Lane 4-Port  
PCI Express® Switch  
®
Highly Integrated Solution  
– Requires no external components  
Device Overview  
The 89HPES4T4 is a member of IDT’s PRECISE™ family of PCI  
Express switching solutions. The PES4T4 is a 4-lane, 4-port peripheral  
chip that performs PCI Express Base switching. It provides connectivity  
and switching functions between a PCI Express upstream port and up to  
four downstream ports and supports switching between downstream  
ports.  
– Incorporates on-chip internal memory for packet buffering and  
queueing  
– Integrates four 2.5 Gbps embedded SerDes with 8B/10B  
encoder/decoder (no separate transceivers needed)  
Reliability, Availability, and Serviceability (RAS) Features  
– Internal end-to-end parity protection on all TLPs ensures data  
integrity even in systems that do not implement end-to-end  
CRC (ECRC)  
– Supports ECRC and Advanced Error Reporting  
– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O  
– Compatible with Hot-Plug I/O expanders used on PC mother-  
boards  
Features  
High Performance PCI Express Switch  
– Four 2.5 Gbps PCI Express lanes  
– Four switch ports  
– x1 Upstream port  
– Three x1 Downstream ports  
Power Management  
– Utilizes advanced low-power design techniques to achieve low  
typical power consumption  
– Low latency cut-through switch architecture  
– Support for Max payload sizes up to 256 bytes  
– One virtual channel  
– Supports PCI Power Management Interface specification (PCI-  
– Eight traffic classes  
PM 1.2)  
– PCI Express Base Specification Revision 1.1 compliant  
Flexible Architecture with Numerous Configuration Options  
– Unused SerDes are disabled.  
– Supports Advanced Configuration and Power Interface Speci-  
fication, Revision 2.0 (ACPI) supporting active link state  
– Automatic lane reversal on all ports  
Testability and Debug Features  
– Built in Pseudo-Random Bit Stream (PRBS) generator  
– Numerous SerDes test modes  
– Automatic polarity inversion on all lanes  
– Ability to load device configuration from serial EEPROM  
Legacy Support  
– Ability to bypass link training and force any link into any mode  
– Provides statistics and performance counters  
– PCI compatible INTx emulation  
– Bus locking  
Block Diagram  
4-Port Switch Core / 4 PCI Express Lanes  
Port  
Frame Buffer  
Route Table  
Arbitration  
Scheduler  
Transaction Layer  
Transaction Layer  
Data Link Layer  
Mux / Demux  
Transaction Layer  
Data Link Layer  
Mux / Demux  
Transaction Layer  
Data Link Layer  
Mux / Demux  
Data Link Layer  
Mux / Demux  
Phy  
Phy  
Phy  
Phy  
Logical  
Layer  
Logical  
Layer  
Logical  
Layer  
Logical  
Layer  
SerDes  
SerDes  
SerDes  
SerDes  
(Port 2)  
(Port 4)  
(Port 0)  
(Port 3)  
Figure 1 Internal Block Diagram  
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.  
1 of 23  
September 7, 2007  
© 2007 Integrated Device Technology, Inc.  
*Notice: The information in this document is subject to change without notice  

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