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89HPES4T4G2ZAAR

更新时间： 2024-02-25 13:43:21
品牌 Logo 应用领域
艾迪悌 - IDT 时钟PC驱动外围集成电路驱动器
页数 文件大小 规格书
30页 741K
描述
PCI Bus Controller, PBGA324, 19 X 19 MM, 1 MM PITCH, ROHS COMPLIANT, FCBGA-324

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89HPES4T4G2ZAAR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：BGA
包装说明：BGA,针数：324
Reach Compliance Code：compliantECCN代码：3A001.A.3
HTS代码：8542.31.00.01风险等级：5.6
其他特性：ALSO REQUIRES 3.3V SUPPLY地址总线宽度：
最大时钟频率：100 MHz驱动器接口标准：IEEE 1149.1
外部数据总线宽度：JESD-30 代码：S-PBGA-B324
JESD-609代码：e3长度：19 mm
端子数量：324最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装形状：SQUARE
封装形式：GRID ARRAY峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：3.42 mm
最大供电电压：1.1 V最小供电电压：0.9 V
标称供电电压：1 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：MATTE TIN端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：30宽度：19 mm
uPs/uCs/外围集成电路类型：BUS CONTROLLER, PCIBase Number Matches：1

89HPES4T4G2ZAAR 数据手册

 浏览型号89HPES4T4G2ZAAR的Datasheet PDF文件第2页浏览型号89HPES4T4G2ZAAR的Datasheet PDF文件第3页浏览型号89HPES4T4G2ZAAR的Datasheet PDF文件第4页浏览型号89HPES4T4G2ZAAR的Datasheet PDF文件第5页浏览型号89HPES4T4G2ZAAR的Datasheet PDF文件第6页浏览型号89HPES4T4G2ZAAR的Datasheet PDF文件第7页 
89HPES4T4G2  
Data Sheet  
Advance Information*  
4-Lane 4-Port  
Gen2 PCI Express® Switch  
®
◆
Legacy Support  
Device Overview  
The 89HPES4T4G2, a 4-lane 4-port Gen2 PCI Express® switch, is a  
member of IDT’s PRECISE™ family of PCI Express switching solutions.  
The PES4T4G2 is a peripheral chip that performs PCI Express base  
switching with a feature set optimized for servers, storage, communica-  
tions, and consumer applications. It provides connectivity and switching  
functions between a PCI Express upstream port and three downstream  
ports or peer-to-peer switching between downstream ports.  
–
–
PCI compatible INTx emulation  
Bus locking  
◆
Highly Integrated Solution  
–
Requires no external components  
–
Incorporates on-chip internal memory for packet buffering and  
queueing  
–
Integrates four 5 Gbps embedded SerDes with 8b/10b  
encoder/decoder (no separate transceivers needed)  
Features  
• Receive equalization (RxEQ)  
Reliability, Availability, and Serviceability (RAS) Features  
◆
High Performance PCI Express Switch  
◆
–
Four Gen2 PCI Express lanes supporting 5 Gbps and  
2.5 Gbps operations  
–
Internal end-to-end parity protection on all TLPs ensures data  
integrity even in systems that do not implement end-to-end  
CRC (ECRC)  
–
Four switch ports  
• One x1 upstream port  
• Three x1 downstream ports  
–
–
–
Supports ECRC and Advanced Error Reporting  
Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O  
Compatible with Hot-Plug I/O expanders used on PC mother-  
boards  
–
–
–
–
Low latency cut-through switch architecture  
Support for Max Payload Size up to 256 bytes  
Supports one virtual channel and eight traffic classes  
PCI Express Base Specification Revision 2.0 compliant  
–
Supports Hot-Swap  
◆
Power Management  
◆
Flexible Architecture with Numerous Configuration Options  
–
Utilizes advanced low-power design techniques to achieve low  
typical power consumption  
–
Automatic lane reversal on all ports  
–
–
Automatic polarity inversion  
Ability to load device configuration from serial EEPROM  
–
Support PCI Power Management Interface specification (PCI-  
PM 2.0)  
Block Diagram  
4-Port Switch Core / 4 Gen2 PCI Express Lanes  
Port  
Frame Buffer  
Route Table  
Arbitration  
Scheduler  
Transaction Layer  
Data Link Layer  
Mux / Demux  
Transaction Layer  
Data Link Layer  
Mux / Demux  
Transaction Layer  
Transaction Layer  
Data Link Layer  
Mux / Demux  
Data Link Layer  
Mux / Demux  
Phy  
Phy  
Phy  
Phy  
Logical  
Layer  
Logical  
Layer  
Logical  
Layer  
Logical  
Layer  
SerDes  
SerDes  
SerDes  
SerDes  
(Port 1)  
(Port 3)  
(Port 0)  
(Port 2)  
Figure 1 Internal Block Diagram  
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.  
1 of 30  
December 4, 2007  
DSC 6928  
© 2007 Integrated Device Technology, Inc.  
*Notice: The information in this document is subject to change without notice  
1234567...30

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