89HPES64H16
Data Sheet
64-Lane 16-Port PCI Express®
System Interconnect Switch
®
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Flexible Architecture with Numerous Configuration Options
Device Overview
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Port arbitration schemes utilizing round robin algorithms
Virtual channels arbitration based on priority
Automatic per port link width negotiation to x8, x4, x2 or x1
Automatic lane reversal on all ports
Automatic polarity inversion on all lanes
Supports locked transactions, allowing use with legacy soft-
ware
The 89HPES64H16 is a member of the IDT PRECISE™ family of
PCI Express® switching solutions. The PES64H16 is a 64-lane, 16-port
system interconnect switch optimized for PCI Express packet switching
in high-performance applications, supporting multiple simultaneous
peer-to-peer traffic flows. Target applications include servers, storage,
communications, and embedded systems.
Features
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Ability to load device configuration from serial EEPROM
Ability to control device via SMBus
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High Performance PCI Express Switch
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Sixteen maximum switch ports
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Highly Integrated Solution
• Eight main ports each of which consists of 8 SerDes
• Each x8 main port can further bifurcate to 2 x4-ports
Sixty-four 2.5 Gbps embedded SerDes
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Requires no external components
Incorporates on-chip internal memory for packet buffering and
queueing
Integrates sixty-four 2.5 Gbps embedded full duplex SerDes,
8B/10B encoder/decoder (no separate transceivers needed)
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• Supports pre-emphasis and receive equalization on per-port
basis
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Delivers 256 Gbps (32 GBps) of aggregate switching capacity
Low-latency cut-through switch architecture
Support for Max Payload Size up to 2048 bytes
Supports two virtual channels and eight traffic classes
PCI Express Base Specification Revision 1.1 compliant
Reliability, Availability, and Serviceability (RAS) Features
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Redundant upstream port failover capability
Supports optional PCI Express end-to-end CRC checking
Block Diagram
x8/x4/x2/x1
x8/x4/x2/x1
x8/x4/x2/x1
x8/x4/x2/x1
SerDes
SerDes
SerDes
SerDes
DL/Transaction Layer
DL/Transaction Layer
DL/Transaction Layer
DL/Transaction Layer
Port
Arbitration
Route Table
16-Port Switch Core
Scheduler
Frame Buffer
DL/Transaction Layer
DL/Transaction Layer
SerDes
DL/Transaction Layer
SerDes
DL/Transaction Layer
SerDes
SerDes
x8/x4/x2/x1
x8/x4/x2/x1
x8/x4/x2/x1
x8/x4/x2/x1
64 PCI Express Lanes
Up to 8 x8 ports or 16 x4 Ports
Figure 1 Internal Block Diagram
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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July 19, 2007
© 2007 Integrated Device Technology, Inc.