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89HPES5T5ZBBCGI

更新时间： 2024-02-20 08:01:44
品牌 Logo 应用领域
瑞萨 - RENESAS 时钟PC外围集成电路
页数 文件大小 规格书
29页 385K
描述
5-Lane 5-Port PCI Express® Switch

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中文翻译

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89HPES5T5ZBBCGI 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：CABGA
包装说明：LBGA, BGA196,14X14,40针数：196
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：1.68
Samacsys Description：CHIP ARRAY BGA 15.0 X 15.0 X 1.0 MM PIT其他特性：ALSO REQUIRES 3.3V SUPPLY
地址总线宽度：总线兼容性：PCI
最大时钟频率：125 MHz外部数据总线宽度：
JESD-30 代码：S-PBGA-B196JESD-609代码：e1
长度：15 mm湿度敏感等级：3
端子数量：196最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：LBGA封装等效代码：BGA196,14X14,40
封装形状：SQUARE封装形式：GRID ARRAY, LOW PROFILE
峰值回流温度（摄氏度）：260电源：1,3.3 V
认证状态：Not Qualified座面最大高度：1.5 mm
子类别：Bus Controllers最大供电电压：1.1 V
最小供电电压：0.9 V标称供电电压：1 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
宽度：15 mmuPs/uCs/外围集成电路类型：BUS CONTROLLER, PCI
Base Number Matches：1

89HPES5T5ZBBCGI 数据手册

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89PES5T5  
Data Sheet  
5-Lane 5-Port PCI Express®  
Switch  
u
Highly Integrated Solution  
– Requires no external components  
Device Overview  
The 89HPES5T5 is a member of IDT’s PRECISE™ family of PCI  
Express switching solutions. The PES5T5 is an 5-lane, 5-port peripheral  
chip that performs PCI Express Base switching. It provides connectivity  
and switching functions between a PCI Express upstream port and up to  
four downstream ports and supports switching between downstream  
ports.  
– Incorporates on-chip internal memory for packet buffering and  
queueing  
– Integrates five 2.5 Gbps embedded SerDes with 8B/10B  
encoder/decoder (no separate transceivers needed)  
Reliability, Availability, and Serviceability (RAS) Features  
– Internal end-to-end parity protection on all TLPs ensures data  
integrity even in systems that do not implement end-to-end  
CRC (ECRC)  
– Supports ECRC and Advanced Error Reporting  
– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O  
– Compatible with Hot-Plug I/O expanders used on PC mother-  
boards  
u
u
u
Features  
u
High Performance PCI Express Switch  
– Five 2.5Gbps PCI Express lanes  
– Five switch ports  
– Upstream port is x1  
– Downstream ports are x1  
Power Management  
– Utilizes advanced low-power design techniques to achieve low  
typical power consumption  
– Low-latency cut-through switch architecture  
– Support for Max Payload Sizes up to 256 bytes  
– One virtual channel  
– Supports PCI Power Management Interface specification (PCI-  
– Eight traffic classes  
PM 1.2)  
– PCI Express Base Specification Revision 1.1 compliant  
Flexible Architecture with Numerous Configuration Options  
– Unused SerDes are disabled.  
u
– Supports Advanced Configuration and Power Interface Speci-  
fication, Revision 2.0 (ACPI) supporting active link state  
– Automatic lane reversal on all ports  
– Automatic polarity inversion  
Testability and Debug Features  
– Ability to load device configuration from serial EEPROM  
Legacy Support  
– Built in Pseudo-Random Bit Stream (PRBS) generator  
– Numerous SerDes test modes  
u
– Ability to read and write any internal register via the SMBus  
– Ability to bypass link training and force any link into any mode  
– Provides statistics and performance counters  
– PCI compatible INTx emulation  
– Bus locking  
Block Diagram  
5-Port Switch Core / 5 PCI Express Lanes  
Port  
Frame Buffer  
Route Table  
Arbitration  
Scheduler  
Transaction Layer  
Data Link Layer  
Mux / Demux  
Transaction Layer  
Data Link Layer  
Transaction Layer  
Data Link Layer  
Transaction Layer  
Data Link Layer  
Transaction Layer  
Data Link Layer  
Mux / Demux  
Mux / Demux  
Mux / Demux  
Mux / Demux  
Phy  
Phy  
Phy  
Phy  
Phy  
Logical  
Layer  
Logical  
Layer  
Logical  
Layer  
Logical  
Layer  
Logical  
Layer  
SerDes  
SerDes  
SerDes  
SerDes  
SerDes  
(Port 2)  
(Port 4)  
(Port 5)  
(Port 0)  
(Port 3)  
Figure 1 Internal Block Diagram  
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.  
1 of 28  
June 18, 2014  
1234567...29

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