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89HPES48H12ZABL

更新时间: 2024-02-15 21:58:37
品牌 Logo 应用领域
艾迪悌 - IDT 总线控制器微控制器和处理器外围集成电路PC时钟
页数 文件大小 规格书
48页 1049K
描述
48-Lane 12-Port PCI Express System Interconnect Switch

89HPES48H12ZABL 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:FCBGA
包装说明:35 X 35 MM, 1 MM PITCH, FCBGA-1156针数:1156
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.82
Is Samacsys:N其他特性:ALSO REQUIRES 3.3V SUPPLY
地址总线宽度:总线兼容性:PCI
最大时钟频率:125 MHz外部数据总线宽度:
JESD-30 代码:S-PBGA-B1156JESD-609代码:e1
长度:35 mm湿度敏感等级:4
端子数量:1156最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA1156,34X34,40
封装形状:SQUARE封装形式:GRID ARRAY
峰值回流温度(摄氏度):245电源:1,3.3 V
认证状态:Not Qualified座面最大高度:3.42 mm
子类别:Bus Controllers最大供电电压:1.1 V
最小供电电压:0.9 V标称供电电压:1 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Silver/Copper (Sn/Ag/Cu)
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:30
宽度:35 mmuPs/uCs/外围集成电路类型:BUS CONTROLLER, PCI
Base Number Matches:1

89HPES48H12ZABL 数据手册

 浏览型号89HPES48H12ZABL的Datasheet PDF文件第2页浏览型号89HPES48H12ZABL的Datasheet PDF文件第3页浏览型号89HPES48H12ZABL的Datasheet PDF文件第4页浏览型号89HPES48H12ZABL的Datasheet PDF文件第5页浏览型号89HPES48H12ZABL的Datasheet PDF文件第6页浏览型号89HPES48H12ZABL的Datasheet PDF文件第7页 
89HPES48H12  
Data Sheet  
48-Lane 12-Port PCI Express®  
System Interconnect Switch  
®
Flexible Architecture with Numerous Configuration Options  
Device Overview  
Port arbitration schemes utilizing round robin algorithms  
Virtual channels arbitration based on priority  
Automatic per port link width negotiation to x8, x4, x2 or x1  
Supports automatic lane reversal on all ports  
Supports automatic polarity inversion on all lanes  
Supports locked transactions, allowing use with legacy soft-  
ware  
The 89HPES48H12 is a member of the IDT PRECISE™ family of  
PCI Express® switching solutions. The PES48H12 is a 48-lane, 12-port  
system interconnect switch optimized for PCI Express packet switching  
in high-performance applications, supporting multiple simultaneous  
peer-to-peer traffic flows. Target applications include servers, storage,  
communications, and embedded systems.  
Features  
Ability to load device configuration from serial EEPROM  
Ability to control device via SMBus  
High Performance PCI Express Switch  
Twelve maximum switch ports  
Highly Integrated Solution  
Six main ports each of which consists of 8 SerDes  
Each x8 main port can further bifurcate to 2 x4-ports  
Forty-eight 2.5 Gbps embedded SerDes  
Requires no external components  
Incorporates on-chip internal memory for packet buffering and  
queueing  
Integrates forty-eight 2.5 Gbps embedded full duplex SerDes,  
8B/10B encoder/decoder (no separate transceivers needed)  
Supports pre-emphasis and receive equalization on per-port  
basis  
Delivers 192 Gbps (24 GBps) of aggregate switching capacity  
Low-latency cut-through switch architecture  
Support for Max Payload Size up to 2048 bytes  
Supports two virtual channels and eight traffic classes  
PCI Express Base Specification Revision 1.1 compliant  
Reliability, Availability, and Serviceability (RAS) Features  
Redundant upstream port failover capability  
Supports optional PCI Express end-to-end CRC checking  
Internal end-to-end parity protection on all TLPs ensures data  
integrity even in systems that do not implement end-to-end  
CRC (ECRC)  
Block Diagram  
x8/x4/x2/x1  
x8/x4/x2/x1  
x8/x4/x2/x1  
SerDes  
SerDes  
SerDes  
DL/Transaction Layer  
DL/Transaction Layer  
DL/Transaction Layer  
Port  
Arbitration  
Route Table  
Frame Buffer  
12-Port Switch Core  
Scheduler  
DL/Transaction Layer  
SerDes  
DL/Transaction Layer  
SerDes  
DL/Transaction Layer  
SerDes  
x8/x4/x2/x1  
x8/x4/x2/x1  
x8/x4/x2/x1  
48 PCI Express Lanes  
Up to 6 x8 ports or 12 x4 Ports  
Figure 1 Internal Block Diagram  
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.  
1 of 48  
July 19, 2007  
DSC 6925  
© 2007 Integrated Device Technology, Inc.  

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