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89HPES24T61ZCBXG8 PDF预览

89HPES24T61ZCBXG8

更新时间： 2024-09-25 20:06:31
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
33页 493K
描述
Bus Controller, PBGA420

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中文翻译

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89HPES24T61ZCBXG8 技术参数

是否Rohs认证： 符合生命周期：Active
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.76
JESD-30 代码：S-PBGA-B420JESD-609代码：e1
湿度敏感等级：3端子数量：420
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA420,26X26,40封装形状：SQUARE
封装形式：GRID ARRAY电源：3.3 V
认证状态：Not Qualified子类别：Bus Controllers
标称供电电压：3.3 V表面贴装：YES
温度等级：COMMERCIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOMBase Number Matches：1

89HPES24T61ZCBXG8 数据手册

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89HPES24T6  
Data Sheet  
24-Lane 6-Port  
PCI Express® Switch  
®
‹
Flexible Architecture with Numerous Configuration Options  
Device Overview  
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Automatic per port link width negotiation to x8, x4, x2 or x1  
Automatic lane reversal on all ports  
Automatic polarity inversion on all lanes  
The 89HPES24T6 is a member of the IDT PRECISE™ family of PCI  
Express® switching solutions. The PES24T6 is a 24-lane, 6-port periph-  
eral chip that performs PCI Express packet switching with a feature set  
optimized for high performance applications such as servers, storage,  
and communications/networking. It provides connectivity and switching  
functions between a PCI Express upstream port and up to five down-  
stream ports and supports switching between downstream ports.  
–
–
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Ability to load device configuration from serial EEPROM  
‹
Legacy Support  
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PCI compatible INTx emulation  
Bus locking  
Highly Integrated Solution  
–
‹
Features  
–
–
Requires no external components  
Incorporates on-chip internal memory for packet buffering and  
queueing  
Integrates twenty-four 2.5 Gbps embedded SerDes with 8B/  
10B encoder/decoder (no separate transceivers needed)  
‹
High Performance PCI Express Switch  
–
–
–
–
–
–
–
–
–
Twenty-four 2.5 Gbps PCI Express lanes  
Six switch ports  
–
Upstream port configurable up to x8  
Downstream ports configurable up to x8  
Low-latency cut-through switch architecture  
Support for Max Payload Size up to 2048 bytes  
One virtual channel  
‹
Reliability, Availability, and Serviceability (RAS) Features  
–
–
Supports ECRC and Advanced Error Reporting  
Internal end-to-end parity protection on all TLPs ensures data  
integrity even in systems that do not implement end-to-end  
CRC (ECRC)  
Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O  
Compatible with Hot-Plug I/O expanders used on PC and  
server motherboards  
Eight traffic classes  
PCI Express Base Specification Revision 1.1 compliant  
–
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Block Diagram  
6-Port Switch Core / 24 PCI Express Lanes  
Port  
Frame Buffer  
Route Table  
Arbitration  
Scheduler  
Transaction Layer  
Data Link Layer  
Transaction Layer  
Data Link Layer  
Transaction Layer  
Data Link Layer  
Multiplexer / Demultiplexer  
Multiplexer / Demultiplexer  
Multiplexer / Demultiplexer  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
SerDes SerDes  
SerDes  
SerDes SerDes  
SerDes  
SerDes SerDes  
SerDes  
SerDes  
SerDes  
SerDes  
(Port 1)  
Figure 1 Internal Block Diagram  
(Port 5)  
(Port 0)  
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.  
1 of 33  
April 23, 2008  
DSC 6923  
© 2008 Integrated Device Technology, Inc.  
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