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74VHCT126 PDF预览

74VHCT126

更新时间: 2024-11-25 01:01:39
品牌 Logo 应用领域
安世 - NEXPERIA /
页数 文件大小 规格书
15页 601K
描述
Quad buffer/line driver; 3-state

74VHCT126 数据手册

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74VHC126; 74VHCT126  
Quad buffer/line driver; 3-state  
Rev. 01 — 13 August 2009  
Product data sheet  
1. General description  
The 74VHC126; 74VHCT126 are high-speed Si-gate CMOS devices and are pin  
compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with  
JEDEC standard No. 7-A.  
The 74VHC126; 74VHCT126 provide four non-inverting buffer/line drivers with 3-state  
outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE).  
A LOW-level at pin nOE causes the outputs to assume a high-impedance OFF-state.  
The 74VHC126; 74VHCT126 are identical to the 74VHC125; 74VHCT125 but have active  
HIGH output enable inputs.  
2. Features  
I Balanced propagation delays  
I All inputs have Schmitt-trigger action  
I Inputs accept voltages higher than VCC  
I Input levels:  
N The 74VHC126 operates with CMOS input level  
N The 74VHCT126 operates with TTL input level  
I ESD protection:  
N HBM JESD22-A114E exceeds 2000 V  
N MM JESD22-A115-A exceeds 200 V  
N CDM JESD22-C101C exceeds 1000 V  
I Multiple package options  
I Specified from 40 °C to +85 °C and from 40 °C to +125 °C  

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