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74VHCT126A PDF预览

74VHCT126A

更新时间: 2024-11-23 22:56:23
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意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
8页 63K
描述
QUAD BUS BUFFERS 3-STATE

74VHCT126A 数据手册

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74VHCT126A  
QUAD BUS BUFFERS (3-STATE)  
PRELIMINARY DATA  
HIGH SPEED:tPD =5 ns (TYP.) atVCC =5V  
LOW POWER DISSIPATION:  
I
CC =4 µA (MAX.) at TA =25 oC  
COMPATIBLEWITH TTL OUTPUTS:  
VIH =2V (MIN), VIL = 0.8V(MAX)  
POWERDOWN PROTECTIONON INPUTS&  
OUTPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL = 8 mA (MIN)  
BALANCEDPROPAGATIONDELAYS:  
tPLH tPHL  
OPERATING VOLTAGERANGE:  
SOP  
TSSOP  
ORDER CODES  
TUBE  
PACKAGE  
SOP  
T & R  
74VHCT126AM 74VHCT126AMTR  
74VHCT126ATTR  
TSSOP  
This device requires the 3-STATE control input G  
to be set low to place the output into the high  
impedance state.  
Power down protection is provided on all inputs  
and outputs and 0 to 7V can be accepted on  
inputs with no regard to the supply voltage. This  
device can be used to interface 5V to 3V.  
VCC (OPR)= 4.5V to 5.5V  
PIN AND FUNCTION COMPATIBLEWITH  
74 SERIES126  
IMPROVED LATCH-UP IMMUNITY  
LOWNOISE:VOLP = 0.8V(Max.)  
DESCRIPTION  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
The 74VHCT126A is an advanced high-speed  
CMOS QUAD BUS BUFFERS fabricated with  
sub-micron silicon gate and double-layer metal  
wiring C2MOS technology.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/8  
March 2000  

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