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74VHCT132A

更新时间： 2024-11-23 22:56:23

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		输入元件
页数	文件大小	规格书
7页	56K
描述
QUAD 2-INPUT SCHMITT NAND GATE

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中文翻译

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数据手册

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74VHCT132A 数据手册

74VHCT132A

QUAD 2-INPUT SCHMITT NAND GATE

PRELIMINARY DATA

■

HIGH SPEED:t_PD=6.5ns (TYP.) atV_CC= 5V

LOW POWER DISSIPATION:

I_CC=2 µA (MAX.) at T_A=25 ^oC

TYPICAL HYSTERESIS:0.7Vat V_CC= 4.5V

POWERDOWN PROTECTIONON INPUTS&

OUTPUTS

■

SOP

TSSOP

■

SYMMETRICAL OUTPUT IMPEDANCE:

|I_OH| = I_OL= 8 mA (MIN)

BALANCEDPROPAGATIONDELAYS:

t_PLHt_PHL

ORDER CODES

TUBE

PACKAGE

SOP

T & R

74VHCT132AM 74VHCT132AMTR

74VHCT132ATTR

TSSOP

OPERATING VOLTAGERANGE:

V_CC(OPR)= 4.5V to 5.5V

inputs with no regard to the supply voltage. This

device can be used to interface 5V to 3V.

Pin configuration and function are the same as

those of the VHCT00A but the VHCT132A has

hysteresis.

PIN AND FUNCTION COMPATIBLEWITH

74 SERIES132

IMPROVED LATCH-UP IMMUNITY

LOWNOISE:V_OLP= 0.8V(Max.)

■

This together with its schmitt trigger function

allows it to be used on line receivers with slow

rise/fall input signals.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

DESCRIPTION

The 74VHCT132A is an advanced high-speed

CMOS QUAD 2-INPUT SCHMITT NAND GATE

fabricated with sub-micron silicon gate and

double-layermetal wiring C²MOS technology.

Power down protection is provided on all inputs

and outputs and 0 to 7V can be accepted on

PIN CONNECTION AND IEC LOGIC SYMBOLS

1/7

February 2000

12 3 4 5 6 7

中文翻译

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型号	品牌	获取价格	描述	数据表
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74VHCT132ATTR	STMICROELECTRONICS	获取价格	QUAD 2-INPUT SCHMITT NAND GATE
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