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74VHCT138A_07 PDF预览

74VHCT138A_07

更新时间: 2024-11-24 05:05:55
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 解码器解复用器
页数 文件大小 规格书
12页 308K
描述
3-to-8 Decoder/Demultiplexer

74VHCT138A_07 数据手册

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74VHCT138A  
3 TO 8 LINE DECODER (INVERTING)  
HIGH SPEED: t = 7.6 ns (TYP.) at V = 5V  
PD CC  
LOW POWER DISSIPATION:  
I
= 4 µA (MAX.) at T =25°C  
CC  
A
COMPATIBLE WITH TTL OUTPUTS:  
= 2V (MIN.), V = 0.8V (MAX)  
POWER DOWN PROTECTION ON INPUTS  
& OUTPUTS  
V
IH  
IL  
SOP  
TSSOP  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 8 mA (MIN)  
OH  
OL  
Table 1: Order Codes  
PACKAGE  
BALANCED PROPAGATION DELAYS:  
t
t
PLH  
PHL  
OPERATING VOLTAGE RANGE:  
(OPR) = 4.5V to 5.5V  
SOP  
74VHCT138AMTR  
74VHCT138ATTR  
V
CC  
TSSOP  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 138  
IMPROVED LATCH-UP IMMUNITY  
The three enable inputs are provided to ease  
cascade connection and application of address  
decoders for memory systems.  
LOW NOISE: V  
= 0.8V (MAX.)  
OLP  
Power down protection is provided on all inputs  
and outputs and 0 to 7V can be accepted on  
inputs with no regard to the supply voltage. This  
device can be used to interface 5V to 3V since all  
inputs are equipped with TTL threshold.  
DESCRIPTION  
The 74VHCT138A is an advanced high-speed  
CMOS 3 TO 8 LINE DECODER (INVERTING)  
fabricated with sub-micron silicon gate and  
2
double-layer metal wiring C MOS technology.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
If the device is enabled, 3 binary select inputs (A,  
B, and C) determine which one of the outputs will  
go low. When enable input G1 is held low or either  
G2A or G2B is held high, the decoding function is  
inhibited and all the 8 outputs go to high.  
Figure 1: Pin Connection And IEC Logic Symbols  
Rev. 3  
1/12  
December 2004  

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