74VHCT139ATTR

更新时间： 2024-11-11 22:39:19

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		解码器解复用器
页数	文件大小	规格书
8页	65K
描述
DUAL 2 TO 4 DECODER/DEMULTIPLEXER

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中文翻译

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数据手册

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74VHCT139ATTR 数据手册

74VHCT139A

DUAL 2 TO 4 DECODER/DEMULTIPLEXER

PRELIMINARY DATA

■

HIGH SPEED:t_PD=7.2ns (TYP.) atV_CC= 5V

LOW POWER DISSIPATION:

I_CC=4 µA (MAX.) at T_A=25 ^oC

COMPATIBLEWITH TTL OUTPUTS:

V_IH=2V (MIN), V_IL= 0.8V(MAX)

POWERDOWN PROTECTIONON INPUTS&

OUTPUTS

SYMMETRICAL OUTPUT IMPEDANCE:

|I_OH| = I_OL= 8 mA (MIN)

BALANCEDPROPAGATIONDELAYS:

t_PLHt_PHL

■

SOP

TSSOP

ORDER CODES

TUBE

PACKAGE

SOP

T & R

74VHCT139AM 74VHCT139AMTR

74VHCT139ATTR

TSSOP

OPERATING VOLTAGERANGE:

V_CC(OPR)= 4.5V to 5.5V

PIN AND FUNCTION COMPATIBLEWITH

74 SERIES139

gating or as a data input for demultiplexing

applications. While the enable input is held high,

all four outputs are high independently of the

other inputs.

IMPROVED LATCH-UP IMMUNITY

Power down protection is provided on all inputs

and outputs and 0 to 7V can be accepted on

inputs with no regard to the supply voltage. This

device can be used to interface 5V to 3V.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

DESCRIPTION

The 74VHCT139A is an advanced high-speed

CMOS DUAL 2 TO

DEMULTIPLEXER fabricated with sub-micron

silicon gate and double-layermetal wiring C²MOS

technology.

LINE DECODER/

The active low enable input can be used for

PIN CONNECTION AND IEC LOGIC SYMBOLS

1/8

March 2000

12 3 4 5 6 7 8

中文翻译

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