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74VHCT138A PDF预览

74VHCT138A

更新时间: 2024-11-23 22:56:23
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
8页 67K
描述
3 TO 8 LINE DECODER INVERTING

74VHCT138A 数据手册

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74VHCT138A  
3 TO 8 LINE DECODER (INVERTING)  
PRELIMINARY DATA  
HIGH SPEED:tPD =7.6ns (TYP.) atVCC = 5V  
LOW POWER DISSIPATION:  
ICC =4 µA (MAX.) at TA =25 oC  
COMPATIBLEWITH TTL OUTPUTS:  
VIH =2V (MIN), VIL = 0.8V(MAX)  
POWERDOWN PROTECTIONON INPUTS&  
OUTPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL = 8 mA (MIN)  
BALANCEDPROPAGATIONDELAYS:  
tPLH tPHL  
SOP  
TSSOP  
ORDER CODES  
TUBE  
PACKAGE  
SOP  
T & R  
74VHCT138AM 74VHCT138AMTR  
74VHCT138ATTR  
TSSOP  
OPERATING VOLTAGERANGE:  
VCC (OPR)= 4.5V to 5.5V  
PIN AND FUNCTION COMPATIBLEWITH  
74 SERIES138  
G2A or G2B is held high, the decoding function is  
inhibited and all the 8 outputsgo to high.  
Three enable inputs are provided to ease  
cascade connection and application of address  
decodersfor memory systems.  
Power down protection is provided on all inputs  
and outputs and 0 to 7V can be accepted on  
inputs with no regard to the supply voltage. This  
device can be used to interface 5V to 3V.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
IMPROVED LATCH-UP IMMUNITY  
LOWNOISE:VOLP = 0.8V(Max.)  
DESCRIPTION  
The 74VHCT138A is an advanced high-speed  
CMOS 3 TO 8 LINE DECODER (INVERTING)  
fabricated with sub-micron silicon gate and  
double-layermetal wiring C2MOS technology.  
If the device is enabled, 3 binary select inputs (A,  
B and C) determine which one of the outputs will  
go low. If enable input G1 is held low or either  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/8  
March 2000  

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