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74VHCT132AMTR PDF预览

74VHCT132AMTR

更新时间: 2024-11-23 22:56:23
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 栅极触发器逻辑集成电路光电二极管输入元件
页数 文件大小 规格书
7页 56K
描述
QUAD 2-INPUT SCHMITT NAND GATE

74VHCT132AMTR 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP14,.25
针数:14Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.4
系列:AHCT/VHCTJESD-30 代码:R-PDSO-G14
JESD-609代码:e4长度:8.65 mm
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
最大I(ol):0.008 A湿度敏感等级:1
功能数量:4输入次数:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:5 VProp。Delay @ Nom-Sup:11.4 ns
传播延迟(tpd):11.4 ns认证状态:Not Qualified
施密特触发器:YES座面最大高度:1.75 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mmBase Number Matches:1

74VHCT132AMTR 数据手册

 浏览型号74VHCT132AMTR的Datasheet PDF文件第2页浏览型号74VHCT132AMTR的Datasheet PDF文件第3页浏览型号74VHCT132AMTR的Datasheet PDF文件第4页浏览型号74VHCT132AMTR的Datasheet PDF文件第5页浏览型号74VHCT132AMTR的Datasheet PDF文件第6页浏览型号74VHCT132AMTR的Datasheet PDF文件第7页 
74VHCT132A  
QUAD 2-INPUT SCHMITT NAND GATE  
PRELIMINARY DATA  
HIGH SPEED:tPD =6.5ns (TYP.) atVCC = 5V  
LOW POWER DISSIPATION:  
ICC =2 µA (MAX.) at TA =25 oC  
TYPICAL HYSTERESIS:0.7Vat VCC = 4.5V  
POWERDOWN PROTECTIONON INPUTS&  
OUTPUTS  
SOP  
TSSOP  
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL = 8 mA (MIN)  
BALANCEDPROPAGATIONDELAYS:  
tPLH tPHL  
ORDER CODES  
TUBE  
PACKAGE  
SOP  
T & R  
74VHCT132AM 74VHCT132AMTR  
74VHCT132ATTR  
TSSOP  
OPERATING VOLTAGERANGE:  
VCC (OPR)= 4.5V to 5.5V  
inputs with no regard to the supply voltage. This  
device can be used to interface 5V to 3V.  
Pin configuration and function are the same as  
those of the VHCT00A but the VHCT132A has  
hysteresis.  
PIN AND FUNCTION COMPATIBLEWITH  
74 SERIES132  
IMPROVED LATCH-UP IMMUNITY  
LOWNOISE:VOLP = 0.8V(Max.)  
This together with its schmitt trigger function  
allows it to be used on line receivers with slow  
rise/fall input signals.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
DESCRIPTION  
The 74VHCT132A is an advanced high-speed  
CMOS QUAD 2-INPUT SCHMITT NAND GATE  
fabricated with sub-micron silicon gate and  
double-layermetal wiring C2MOS technology.  
Power down protection is provided on all inputs  
and outputs and 0 to 7V can be accepted on  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/7  
February 2000  

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