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74VHC4040CW PDF预览

74VHC4040CW

更新时间： 2024-09-16 13:02:47
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 计数器
页数 文件大小 规格书
9页 328K
描述
Binary Counter, AHC/VHC Series, Asynchronous, Negative Edge Triggered, 12-Bit, Up Direction, CMOS

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74VHC4040CW 技术参数

生命周期：Obsolete包装说明：DIE,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.67计数方向：UP
系列：AHC/VHCJESD-30 代码：R-XUUC-N16
负载/预设输入：YES逻辑集成电路类型：BINARY COUNTER
工作模式：ASYNCHRONOUS位数：12
功能数量：1端子数量：16
封装主体材料：UNSPECIFIED封装代码：DIE
封装形状：RECTANGULAR封装形式：UNCASED CHIP
传播延迟（tpd）：15.4 ns认证状态：Not Qualified
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：2 V
表面贴装：YES技术：CMOS
端子形式：NO LEAD端子位置：UPPER
触发器类型：NEGATIVE EDGE最小 fmax：150 MHz
Base Number Matches：1

74VHC4040CW 数据手册

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May 2007  
74VHC4040  
tm  
12-Stage Binary Counter  
Features  
General Description  
■ High speed; f  
= 210MHz at V = 5V  
The VHC4040 is an advanced high-speed CMOS device  
fabricated with silicon gate CMOS technology. It  
achieves the high-speed operation similar to equivalent  
Bipolar Schottky TTL while maintaining the CMOS low  
power dissipation. The VHC4040 is a 12-stage counter  
which increments on the negative edge of the input clock  
and all outputs are reset to a low level by applying a  
logical high on the reset input. An input protection circuit  
insures that 0V to 7V can be applied to the inputs without  
regard to the supply voltage. This device can be used to  
interface 5V to 3V systems and two supply systems such  
as battery backup. This circuit prevents device destruc-  
tion due to mismatched supply and input voltages.  
MAX  
CC  
■ Low power dissipation: I = 4µA (Max.) at T = 25°C  
CC  
A
■ High noise immunity: V  
= V  
= 28% V (Min.)  
NIH  
NIL CC  
■ Power down protection is provided on all inputs  
■ Wide operating voltage range: V (Opr.) = 2V – 5.5V  
CC  
■ Low noise: V  
= 0.8V (Max.)  
OLP  
■ Pin and function compatible with 74HC4040  
Ordering Information  
Package  
Order Number  
74VHC4040M  
Number  
Package Description  
M16A  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow  
74VHC4040MTC  
MTC16  
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,  
4.4mm Wide  
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the  
ordering number.  
Connection Diagram  
Pin Descriptions  
Pin Names  
Description  
Q –Q  
Flip-Flop Outputs  
0
11  
CP  
Negative Edged Triggered Clock  
Master Reset  
MR  
©1993 Fairchild Semiconductor Corporation  
74VHC4040 Rev. 1.3  
www.fairchildsemi.com  
1234567...9

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