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74VHC4040FT PDF预览

74VHC4040FT

更新时间: 2024-11-21 14:56:19
品牌 Logo 应用领域
东芝 - TOSHIBA /
页数 文件大小 规格书
10页 195K
描述
12-Stage Binary Counter, TSSOP16B

74VHC4040FT 数据手册

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74VHC4040FT  
CMOS Digital Integrated Circuits Silicon Monolithic  
74VHC4040FT  
1. Functional Description  
12-Stage Ripple Carry Binary Counter  
2. General  
The 74VHC4040FT is an advanced high speed CMOS 12-STAGE BINARY COUNTER/DIVIDER fabricated with  
silicon gate C2MOS technology.  
It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS  
low power dissipation.  
Setting CLR to high resets the counter to low.  
A negative transition on the CK input brings one increment into the counter.  
This counter provides all divided output stages, and at Q12, a 1/4096 divided frequency will be output.  
An input protection circuit ensures that 0 to 5.5 V can be applied to the input pins without regard to the supply  
voltage. This device can be used to interface 5 V to 3 V systems and two supply systems such as battery back up.  
This circuit prevents device destruction due to mismatched supply and input voltages.  
3. Features  
(1) AEC-Q100 (Rev. H) (Note 1)  
(2) Wide operating temperature range: Topr = -40 to 125  
(3) High speed: fMAX = 210 MHz (typ.) at VCC = 5 V  
(4) Low power dissipation: ICC = 4.0 µA (max) at Ta = 25   
(5) High noise immunity: VNIH = VNIL = 28 % VCC (min)  
(6) Power-down protection is provided on all inputs.  
(7) Balanced propagation delays: tPLH tPHL  
(8) Wide operating voltage range: VCC(opr) = 2.0 V to 5.5 V  
(9) Low noise: VOLP = 1.5 V (max)  
(10) Pin and function compatible with 74HC4040  
Note 1: This device is compliant with the reliability requirements of AEC-Q100. For details, contact your Toshiba sales  
representative.  
4. Packaging  
TSSOP16B  
Start of commercial production  
2014-10  
©2016 Toshiba Corporation  
2017-02-13  
Rev.4.0  
1

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