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74VCX163245 PDF预览

74VCX163245

更新时间: 2024-11-08 22:45:59
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飞兆/仙童 - FAIRCHILD /
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9页 103K
描述
Low Voltage 16-Bit Dual Supply Translating Transceiver with 3-STATE Outputs

74VCX163245 数据手册

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March 2000  
Revised June 2005  
74VCX163245  
Low Voltage 16-Bit Dual Supply Translating Transceiver  
with 3-STATE Outputs  
General Description  
Features  
Bidirectional interface between busses ranging from  
The VCX163245 is a dual supply, 16-bit translating trans-  
ceiver that is designed for 2 way asynchronous communi-  
cation between busses at different supply voltages by  
providing true signal translation. The supply rails consist of  
1.65V to 3.6V  
Supports Live Insertion and Withdrawal (Note 1)  
Static Drive (IOH/IOL  
)
VCCA, which is a higher potential rail operating at 2.3V to  
24 mA @ 3.0V VCC  
18 mA @ 2.3V VCC  
6 mA @ 1.65V VCC  
3.6V and VCCB, which is the lower potential rail operating at  
1.65V to 2.7V. (VCCB must be less than or equal to VCCA  
for proper device operation). This dual supply design  
allows for translation from 1.8V to 2.5V busses to busses at  
a higher potential, up to 3.3V.  
Uses patented Quiet Series noise/EMI reduction  
circuitry  
The Transmit/Receive (T/R) input determines the direction  
of data flow. Transmit (active-HIGH) enables data from A  
Ports to B Ports; Receive (active-LOW) enables data from  
B Ports to A Ports. The Output Enable (OE) input, when  
HIGH, disables both A and B Ports by placing them in a  
High-Z condition. The A Port interfaces with the higher volt-  
age bus (2.7V to 3.3V); The B Port interfaces with the lower  
voltage bus (1.8V to 2.5V). Also the VCX163245 is  
designed so that the control pins (T/Rn, OEn) are supplied  
Functionally compatible with 74 series 16245  
Latchup performance exceeds 300 mA  
ESD performance:  
Human Body Model 2000V  
Machine model 200V  
Also packaged in plastic Fine-Pitch Ball Grid Array  
(FBGA)  
by VCCB  
.
The 74VCX163245 is suitable for mixed voltage applica-  
tions such as notebook computers using a 1.8V CPU and  
3.3V peripheral components. It is fabricated with an  
Advanced CMOS technology to achieve high speed opera-  
tion while maintaining low CMOS power dissipation.  
Note 1: To ensure the high impedance state during power up or power  
down, OE should be tied to V  
through a pull up resistor. The minimum  
CCB  
n
value of the resistor is determined by the current sourcing capability of the  
driver.  
Ordering Code:  
Order Number  
Package Number  
Package Description  
74VCX163245G  
(Note 2)(Note 3)  
BGA54A  
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide  
74VCX163245MTD  
(Note 3)  
MTD48  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Note 2: Ordering code “G” indicates Trays.  
Note 3: Device also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Diagram  
Quiet Series is a trademark of Fairchild Semiconductor Corporation.  
© 2005 Fairchild Semiconductor Corporation  
ds500168  
www.fairchildsemi.com  

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