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74VCX16373/D PDF预览

74VCX16373/D

更新时间: 2024-11-24 23:24:35
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其他 - ETC 锁存器
页数 文件大小 规格书
12页 149K
描述
Low-Voltage 1.8/2.5/3.3V 16-Bit Transparent Latch

74VCX16373/D 数据手册

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74VCX16373  
Low-Voltage 1.8/2.5/3.3V  
16-Bit Transparent Latch  
With 3.6V–Tolerant Inputs and Outputs  
(3–State, Non–Inverting)  
The 74VCX16373 is an advanced performance, non–inverting  
16–bit transparent latch. It is designed for very high–speed, very  
low–power operation in 1.8V, 2.5V or 3.3V systems. The VCX16373  
is byte controlled, with each byte functioning identically, but  
independently. Each byte has separate Output Enable and Latch  
Enable inputs. These control pins can be tied together for full 16–bit  
operation.  
http://onsemi.com  
MARKING DIAGRAM  
48  
48  
When operating at 2.5V (or 1.8V) the part is designed to tolerate  
voltages it may encounter on either inputs or outputs when interfacing  
to 3.3V busses. It is guaranteed to be over–voltage tolerant to 3.6V.  
The 74VCX16373 contains 16 D–type latches with 3–state  
3.6V–tolerant outputs. When the Latch Enable (LEn) inputs are  
HIGH, data on the Dn inputs enters the latches. In this condition, the  
latches are transparent, (a latch output will change state each time its D  
input changes). When LE is LOW, the latch stores the information that  
was present on the D inputs a setup time preceding the  
HIGH–to–LOW transition of LE. The 3–state outputs are controlled  
by the Output Enable (OEn) inputs. When OE is LOW, the outputs are  
enabled. When OE is HIGH, the standard outputs are in the high  
impedance state, but this does not interfere with new data entering into  
the latches.  
74VCX16373DT  
AWLYYWW  
1
TSSOP–48  
DT SUFFIX  
CASE 1201  
1
= Assembly Location  
A
WL = Wafer Lot  
YY = Year  
WW = Work Week  
PIN NAMES  
Pins  
Function  
Designed for Low Voltage Operation: V = 1.65–3.6V  
CC  
3.6V Tolerant Inputs and Outputs  
High Speed Operation: 3.0ns max for 3.0 to 3.6V  
3.9ns max for 2.3 to 2.7V  
OEn  
LEn  
D0–D15  
O0–O15  
Output Enable Inputs  
Latch Enable Inputs  
Inputs  
Outputs  
6.8ns max for 1.65 to 1.95V  
Static Drive: ±24mA Drive at 3.0V  
±18mA Drive at 2.3V  
±6mA Drive at 1.65V  
Supports Live Insertion and Withdrawal  
ORDERING INFORMATION  
I  
Specification Guarantees High Impedance When V = 0V  
OFF  
CC  
Near Zero Static Supply Current in All Three Logic States (20µA)  
Substantially Reduces System Power Requirements  
Device  
74VCX16373DT  
74VCX16373DTR  
Package  
TSSOP  
TSSOP  
Shipping  
39 / Rail  
Latchup Performance Exceeds ±250mA @ 125°C  
2500 / Reel  
ESD Performance: Human Body Model >2000V; Machine Model  
>200V  
Semiconductor Components Industries, LLC, 2001  
1
Publication Order Number:  
January, 2001 – Rev. 1  
74VCX16373/D  

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