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74VCX164245G PDF预览

74VCX164245G

更新时间： 2024-11-05 04:47:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器逻辑集成电路
页数 文件大小 规格书
9页 102K
描述
Low Voltage 16-Bit Dual Supply Translating Transceiver with 3-STATE Outputs

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中文翻译

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74VCX164245G 技术参数

是否无铅： 不含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：LFBGA, BGA54,6X9,32针数：54
Reach Compliance Code：compliant风险等级：5.76
Is Samacsys：N其他特性：1.65V TO 2.7V SUPPLY FOR PORT A; 2.3V TO 3.6V SUPPLY FOR PORT B
控制类型：COMMON CONTROL计数方向：BIDIRECTIONAL
系列：ALVC/VCX/AJESD-30 代码：R-PBGA-B54
JESD-609代码：e0长度：8 mm
负载电容（CL）：30 pF逻辑集成电路类型：BUS TRANSCEIVER
最大I（ol）：0.018 A湿度敏感等级：3
位数：8功能数量：2
端口数量：2端子数量：54
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：LFBGA
封装等效代码：BGA54,6X9,32封装形状：RECTANGULAR
封装形式：GRID ARRAY, LOW PROFILE, FINE PITCH包装方法：RAIL
峰值回流温度（摄氏度）：260电源：1.8/2.5,2.5/3.3 V
Prop。Delay @ Nom-Sup：5.8 ns传播延迟（tpd）：6.2 ns
认证状态：Not Qualified座面最大高度：1.4 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：2.7 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：0.8 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：1.8/2.5V &3.3V宽度：5.5 mm
Base Number Matches：1

74VCX164245G 数据手册

 浏览型号74VCX164245G的Datasheet PDF文件第2页浏览型号74VCX164245G的Datasheet PDF文件第3页浏览型号74VCX164245G的Datasheet PDF文件第4页浏览型号74VCX164245G的Datasheet PDF文件第5页浏览型号74VCX164245G的Datasheet PDF文件第6页浏览型号74VCX164245G的Datasheet PDF文件第7页 
March 2000  
Revised June 2005  
74VCX164245  
Low Voltage 16-Bit Dual Supply Translating Transceiver  
with 3-STATE Outputs  
General Description  
Features  
■ Bidirectional interface between busses ranging from  
The VCX164245 is a dual supply, 16-bit translating trans-  
ceiver that is designed for two way asynchronous commu-  
nication between busses at different supply voltages by  
providing true signal translation. The supply rails consist of  
1.65V to 3.6V  
■ Supports Live Insertion and Withdrawal (Note 1)  
■ Static Drive (IOH/IOL  
)
VCCB, which is the higher potential rail operating at 2.3V to  
24 mA @ 3.0V VCC  
18 mA @ 2.3V VCC  
6 mA @ 1.65V VCC  
3.6V and VCCA, which is the lower potential rail operating at  
1.65V to 2.7V. (VCCA must be less than or equal to VCCB  
for proper device operation.) This dual supply design  
allows for translation from 1.8V to 2.5V busses to busses at  
a higher potential, up to 3.3V.  
■ Uses patented noise/EMI reduction circuitry  
■ Functionally compatible with 74 series 16245  
■ Latchup performance exceeds 300 mA  
■ ESD performance:  
The Transmit/Receive (T/R) input determines the direction  
of data flow. Transmit (active-HIGH) enables data from A  
Ports to B Ports. Receive (active-LOW) enables data from  
B Ports to A Ports. The Output Enable (OE) input, when  
HIGH, disables both A and B Ports by placing them in a  
High-Z condition. The A Port interfaces with the lower volt-  
Human Body Model 2000V  
Machine model 200V  
■ Also packaged in plastic Fine-Pitch Ball Grid Array  
(FBGA)  
age bus (1.8V  
2.5V). The B Port interfaces with the  
higher voltage bus (2.7V 3.3V). Also the VCX164245 is  
designed so that the control pins (T/Rn, OEn) are supplied  
by VCCB  
.
Note 1: To ensure the high impedance state during power up or power  
The 74VCX164245 is suitable for mixed voltage applica-  
tions such as notebook computers using a 1.8V CPU and  
3.3V peripheral components. It is fabricated with an  
Advanced CMOS technology to achieve high speed opera-  
tion while maintaining low CMOS power dissipation.  
down, OE should be tied to V  
through a pull up resistor. The minimum  
CCB  
n
value of the resistor is determined by the current sourcing capability of the  
driver.  
Ordering Code:  
Order Number  
Package Number  
Package Description  
74VCX164245G  
(Note 2)(Note 3)  
BGA54A  
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide  
74VCX164245MTD  
(Note 3)  
MTD48  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Note 2: Ordering Code “G” indicates Trays.  
Note 3: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Diagram  
© 2005 Fairchild Semiconductor Corporation  
DS500159  
www.fairchildsemi.com  
1234567...9

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