5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 总线驱动器/收发器> 74VCX163245MTDX_NL
74VCX163245MTDX_NL PDF预览

74VCX163245MTDX_NL

更新时间： 2024-09-14 13:04:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
9页 103K
描述
Bus Transceiver, ALVC/VCX/A Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, 6.10 MM, MO-153ED, TSSOP-48

阅读下载

中文翻译

获取价格

74VCX163245MTDX_NL 技术参数

是否Rohs认证：符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：6.10 MM, MO-153ED, TSSOP-48
针数：48Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.24
Is Samacsys：N其他特性：2.3V TO 3.6V SUPPLY FOR PORT A; 1.65V TO 2.7V SUPPLY FOR PORT B
控制类型：COMMON CONTROL计数方向：BIDIRECTIONAL
系列：ALVC/VCX/AJESD-30 代码：R-PDSO-G48
JESD-609代码：e3长度：12.5 mm
负载电容（CL）：30 pF逻辑集成电路类型：BUS TRANSCEIVER
最大I（ol）：0.006 A湿度敏感等级：2
位数：8功能数量：2
端口数量：2端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP48,.3,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：260电源：1.8/2.5,2.5/3.3 V
Prop。Delay @ Nom-Sup：5.8 ns传播延迟（tpd）：6.2 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：2.7 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：1.8/2.5V &3.3V宽度：6.1 mm
Base Number Matches：1

74VCX163245MTDX_NL 数据手册

 浏览型号74VCX163245MTDX_NL的Datasheet PDF文件第2页浏览型号74VCX163245MTDX_NL的Datasheet PDF文件第3页浏览型号74VCX163245MTDX_NL的Datasheet PDF文件第4页浏览型号74VCX163245MTDX_NL的Datasheet PDF文件第5页浏览型号74VCX163245MTDX_NL的Datasheet PDF文件第6页浏览型号74VCX163245MTDX_NL的Datasheet PDF文件第7页 
March 2000  
Revised June 2005  
74VCX163245  
Low Voltage 16-Bit Dual Supply Translating Transceiver  
with 3-STATE Outputs  
General Description  
Features  
■ Bidirectional interface between busses ranging from  
The VCX163245 is a dual supply, 16-bit translating trans-  
ceiver that is designed for 2 way asynchronous communi-  
cation between busses at different supply voltages by  
providing true signal translation. The supply rails consist of  
1.65V to 3.6V  
■ Supports Live Insertion and Withdrawal (Note 1)  
■ Static Drive (IOH/IOL  
)
VCCA, which is a higher potential rail operating at 2.3V to  
24 mA @ 3.0V VCC  
18 mA @ 2.3V VCC  
6 mA @ 1.65V VCC  
3.6V and VCCB, which is the lower potential rail operating at  
1.65V to 2.7V. (VCCB must be less than or equal to VCCA  
for proper device operation). This dual supply design  
allows for translation from 1.8V to 2.5V busses to busses at  
a higher potential, up to 3.3V.  
■ Uses patented Quiet Series noise/EMI reduction  
circuitry  
The Transmit/Receive (T/R) input determines the direction  
of data flow. Transmit (active-HIGH) enables data from A  
Ports to B Ports; Receive (active-LOW) enables data from  
B Ports to A Ports. The Output Enable (OE) input, when  
HIGH, disables both A and B Ports by placing them in a  
High-Z condition. The A Port interfaces with the higher volt-  
age bus (2.7V to 3.3V); The B Port interfaces with the lower  
voltage bus (1.8V to 2.5V). Also the VCX163245 is  
designed so that the control pins (T/Rn, OEn) are supplied  
■ Functionally compatible with 74 series 16245  
■ Latchup performance exceeds 300 mA  
■ ESD performance:  
Human Body Model 2000V  
Machine model 200V  
■ Also packaged in plastic Fine-Pitch Ball Grid Array  
(FBGA)  
by VCCB  
.
The 74VCX163245 is suitable for mixed voltage applica-  
tions such as notebook computers using a 1.8V CPU and  
3.3V peripheral components. It is fabricated with an  
Advanced CMOS technology to achieve high speed opera-  
tion while maintaining low CMOS power dissipation.  
Note 1: To ensure the high impedance state during power up or power  
down, OE should be tied to V  
through a pull up resistor. The minimum  
CCB  
n
value of the resistor is determined by the current sourcing capability of the  
driver.  
Ordering Code:  
Order Number  
Package Number  
Package Description  
74VCX163245G  
(Note 2)(Note 3)  
BGA54A  
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide  
74VCX163245MTD  
(Note 3)  
MTD48  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Note 2: Ordering code “G” indicates Trays.  
Note 3: Device also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Diagram  
Quiet Series is a trademark of Fairchild Semiconductor Corporation.  
© 2005 Fairchild Semiconductor Corporation  
ds500168  
www.fairchildsemi.com  
1234567...9

中文翻译

下载PDF

与74VCX163245MTDX_NL相关器件

型号 品牌 获取价格 描述 数据表
74VCX163245TB STMICROELECTRONICS

获取价格

 		16-BIT DUAL SUPPLY BUS TRANSCEIVER LEVEL TRANSLATOR
74VCX163245TBR STMICROELECTRONICS

获取价格

 		16-BIT DUAL SUPPLY BUS TRANSCEIVER LEVEL TRANSLATOR
74VCX163245TTR STMICROELECTRONICS

获取价格

 		16-BIT DUAL SUPPLY BUS TRANSCEIVER LEVEL TRANSLATOR
74VCX16373 FAIRCHILD

获取价格

 		Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs
74VCX16373 ONSEMI

获取价格

 		Low−Voltage 1.8/2.5/3.3V 16−Bit Transparent Latch
74VCX16373/D ETC

获取价格

 		Low-Voltage 1.8/2.5/3.3V 16-Bit Transparent Latch
74VCX16373_06 ONSEMI

获取价格

 		Low−Voltage 1.8/2.5/3.3V 16−Bit Transparent Latch
74VCX16373DT ONSEMI

获取价格

 		Low−Voltage 1.8/2.5/3.3V 16−Bit Transparent Latch
74VCX16373DTR ONSEMI

获取价格

 		Low−Voltage 1.8/2.5/3.3V 16−Bit Transparent Latch
74VCX16373G ONSEMI

获取价格

 		暂无描述

与74VCX163245MTDX_NL相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证