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74VCX16373 PDF预览

74VCX16373

更新时间: 2024-09-13 22:34:43
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 锁存器
页数 文件大小 规格书
10页 127K
描述
Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs

74VCX16373 数据手册

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October 1997  
Revised June 2005  
74VCX16373  
Low Voltage 16-Bit Transparent Latch  
with 3.6V Tolerant Inputs and Outputs  
General Description  
Features  
1.2V to 3.6V VCC supply operation  
The VCX16373 contains sixteen non-inverting latches with  
3-STATE outputs and is intended for bus oriented applica-  
tions. The device is byte controlled. The flip-flops appear to  
be transparent to the data when the Latch Enable (LE) is  
HIGH. When LE is LOW, the data that meets the setup time  
is latched. Data appears on the bus when the Output  
Enable (OE) is LOW. When OE is HIGH, the outputs are in  
a high impedance state.  
3.6V tolerant inputs and outputs  
tPD (In to On)  
3.0 ns max for 3.0V to 3.6V VCC  
Power-off high impedance inputs and outputs  
Support live insertion and withdrawal (Note 1)  
Static Drive (IOH/IOL  
)
The 74VCX16373 is designed for low voltage (1.2V to  
3.6V) VCC applications with I/O compatibility up to 3.6V.  
24 mA @ 3.0V VCC  
The 74VCX16373 is fabricated with an advanced CMOS  
technology to achieve high speed operation while maintain-  
ing low CMOS power dissipation.  
Uses patented noise/EMI reduction circuitry  
Latch-up performance exceeds 300 mA  
ESD performance:  
Human body model 2000V  
Machine model 200V  
Also packaged in plastic Fine-Pitch Ball Grid Array  
(FBGA) (Preliminary)  
Note 1: To ensure the high-impedance state during power up or power  
down, OE should be tied to V  
through a pull-up resistor; the minimum  
CC  
value of the resistor is determined by the current-sourcing capability of the  
driver.  
Ordering Code:  
Order Number  
Package Number  
Package Description  
74VCX16373G  
(Note 2)(Note 3)  
BGA54A  
(Preliminary)  
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide  
74VCX16373MTD  
(Note 3)  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
MTD48  
Note 2: Ordering Code “G” indicates Trays.  
Note 3: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbol  
© 2005 Fairchild Semiconductor Corporation  
DS500065  
www.fairchildsemi.com  

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