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74LVX74 PDF预览

74LVX74

更新时间: 2024-11-13 22:15:07
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器
页数 文件大小 规格书
7页 96K
描述
Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop

74LVX74 数据手册

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May 1993  
Revised February 2005  
74LVX74  
Low Voltage Dual D-Type Positive Edge-Triggered  
Flip-Flop  
Asynchronous Inputs:  
General Description  
The LVX74 is a dual D-type flip-flop with Asynchronous  
LOW input to SD (Set) sets Q to HIGH level  
LOW input to CD (Clear) sets Q to LOW level  
Clear and Set inputs and complementary (Q, Q) outputs.  
Information at the input is transferred to the outputs on the  
positive edge of the clock pulse. After the Clock Pulse input  
threshold voltage has been passed, the Data input is  
locked out and information present will not be transferred to  
the outputs until the next rising edge of the Clock Pulse  
input.  
Clear and Set are independent of clock  
Simultaneous LOW on CD and SD makes both Q and Q  
HIGH  
Features  
Input voltage level translation from 5V to 3V  
Ideal for low power/low noise 3.3V applications  
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
Ordering Code:  
Package  
Order Number  
Package Description  
Number  
74LVX74M  
M14A  
M14D  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
74LVX74SJ  
74LVX74MTC  
MTC14  
MTC14  
74LVX74MTCX_NL  
(Note 1)  
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm  
Wide  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Pb-Free package per JEDEC J-STD-020B.  
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.  
Connection Diagram  
Pin Descriptions  
Pin Names  
D1, D2  
Description  
Data Inputs  
CP1, CP2  
CD1, CD2  
Clock Pulse Inputs  
Direct Clear Inputs  
Direct Set Inputs  
Outputs  
SD1, SD2  
Q1, Q1, Q2, Q2  
© 2005 Fairchild Semiconductor Corporation  
DS011606  
www.fairchildsemi.com  

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