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74LVX86MSCX PDF预览

74LVX86MSCX

更新时间: 2024-11-15 13:04:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD
页数 文件大小 规格书
5页 66K
描述
XOR Gate, LV/LV-A/LVX/H Series, 4-Func, 2-Input, CMOS, PDSO14, EIAJ TYPE1, PLASTIC, SSOP-14

74LVX86MSCX 技术参数

生命周期:Obsolete零件包装代码:SSOP
包装说明:LSSOP,针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.5其他特性:INPUTS CAN BE DRIVEN BY 3V OR 5V COMPONENTS
系列:LV/LV-A/LVX/HJESD-30 代码:R-PDSO-G14
长度:5 mm逻辑集成电路类型:XOR GATE
功能数量:4输入次数:2
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, LOW PROFILE, SHRINK PITCH传播延迟(tpd):11 ns
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL宽度:4.4 mm
Base Number Matches:1

74LVX86MSCX 数据手册

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May 1993  
Revised March 1999  
74LVX86  
Low Voltage Quad 2-Input Exclusive-OR Gate  
General Description  
The LVX86 contains four 2-input exclusive-OR gates. The  
inputs tolerate voltages up to 7V allowing the interface of  
5V systems to 3V systems.  
Features  
Input voltage level translation from 5V to 3V  
Ideal for low power/low noise 3.3V applications  
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
Ordering Code:  
Order Number Package Number  
Package Description  
74LVX86M  
M14A  
M14D  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
74LVX86SJ  
74LVX86MTC  
MTC14  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
Pin Descriptions  
Pin Names  
A0–A3  
Description  
Inputs  
B0–B3  
O0–O3  
Inputs  
Outputs  
© 1999 Fairchild Semiconductor Corporation  
DS011605.prf  
www.fairchildsemi.com  

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XOR Gate, LV/LV-A/LVX/H Series, 4-Func, 2-Input, CMOS, PDSO14, 0.150 INCH, MS-120, SOIC-14