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74LVX86MTCX_NL PDF预览

74LVX86MTCX_NL

更新时间: 2024-11-15 13:00:35
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD
页数 文件大小 规格书
5页 66K
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74LVX86MTCX_NL 数据手册

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May 1993  
Revised March 1999  
74LVX86  
Low Voltage Quad 2-Input Exclusive-OR Gate  
General Description  
The LVX86 contains four 2-input exclusive-OR gates. The  
inputs tolerate voltages up to 7V allowing the interface of  
5V systems to 3V systems.  
Features  
Input voltage level translation from 5V to 3V  
Ideal for low power/low noise 3.3V applications  
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
Ordering Code:  
Order Number Package Number  
Package Description  
74LVX86M  
M14A  
M14D  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
74LVX86SJ  
74LVX86MTC  
MTC14  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
Pin Descriptions  
Pin Names  
A0–A3  
Description  
Inputs  
B0–B3  
O0–O3  
Inputs  
Outputs  
© 1999 Fairchild Semiconductor Corporation  
DS011605.prf  
www.fairchildsemi.com  

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