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74LVXC3245MTR PDF预览

74LVXC3245MTR

更新时间: 2024-11-15 03:53:35
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线收发器
页数 文件大小 规格书
14页 349K
描述
OCTAL DUAL SUPPLY BUS TRANSCEIVER

74LVXC3245MTR 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP-24
针数:24Reach Compliance Code:unknown
HTS代码:8542.39.00.01Factory Lead Time:43 weeks 2 days
风险等级:5.22其他特性:PORT A OPERATES AT 4.5V TO 5.5V
控制类型:COMMON CONTROL计数方向:BIDIRECTIONAL
系列:LV/LV-A/LVX/HJESD-30 代码:R-PDSO-G24
JESD-609代码:e4长度:15.4 mm
逻辑集成电路类型:BUS TRANSCEIVER最大I(ol):0.024 A
湿度敏感等级:3位数:8
功能数量:1端口数量:2
端子数量:24最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP24,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):250
电源:3/3.3,3/5 VProp。Delay @ Nom-Sup:9 ns
传播延迟(tpd):9.5 ns认证状态:Not Qualified
座面最大高度:2.65 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED翻译:3V & 3/5V
宽度:7.5 mmBase Number Matches:1

74LVXC3245MTR 数据手册

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74LVXC3245  
OCTAL DUAL SUPPLY BUS TRANSCEIVER  
HIGH SPEED:  
t
= 8ns (MAX.) at T =25°C  
PD  
A
V
= 3.3V, V  
= 5.0V  
CCA  
CCB  
LOW POWER DISSIPATION:  
= I = 5µA(MAX.) at T =25°C  
I
CCA  
CCB  
A
LOW NOISE: V  
=0.3V (TYP.) at  
OLP  
V
=3.3V  
SOP  
TSSOP  
T & R  
CCA  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 24mA (MIN)  
OH  
OL  
Table 1: Order Codes  
PACKAGE  
BALANCED PROPAGATION DELAYS:  
t
t
PLH  
PHL  
OPERATING VOLTAGE RANGE:  
SOP  
74LVXC3245MTR  
74LVXC3245TTR  
V
(OPR)=2.7Vto3.6V(1.2VDataRetention)  
CCA  
TSSOP  
V
(OPR)=2.7Vto5.5V(1.2VDataRetention)  
CCB  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES C3245  
IMPROVED LATCH-UP IMMUNITY  
This IC is intended for two-way asynchronous  
communication between data buses and the  
direction of data transmission is determined by  
DIR input. The enable input G can be used to  
disable the device so that the buses are effectively  
isolated.  
DESCRIPTION  
The 74LVXC3245 is  
a dual supply 8 bit  
configurable low voltage CMOS OCTAL BUS  
TRANSCEIVER fabricated with sub-micron silicon  
The A-port interfaces with the 3V bus, the B-port  
with the 5V bus.  
2
gate and double-layer metal wiring C MOS  
technology. Designed for use as an interface  
between a 3.3V bus and a 3.3V to 5V bus in a  
mixed 3.3V/5V supply systems, it achieves high  
speed operation while maintaining the CMOS low  
power dissipation.  
All inputs are equipped with protection circuits  
against static discharge, giving them 2KV ESD  
immunity and transient excess voltage.  
Figure 1: Pin Connection And IEC Logic Symbols  
Rev. 4  
1/14  
August 2004  

74LVXC3245MTR 替代型号

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