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74LVX86T PDF预览

74LVX86T

更新时间: 2024-01-03 09:41:52
品牌 Logo 应用领域
其他 - ETC 触发器逻辑集成电路石英晶振光电二极管
页数 文件大小 规格书
8页 59K
描述
Quad 2-input Exclusive OR (XOR) Gate

74LVX86T 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP14,.25针数:14
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.4系列:LV/LV-A/LVX/H
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:5 mm负载电容(CL):50 pF
逻辑集成电路类型:XOR GATE最大I(ol):0.004 A
功能数量:4输入次数:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 VProp。Delay @ Nom-Sup:14.5 ns
传播延迟(tpd):21 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:1.2 mm
子类别:Gates最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):2.7 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mmBase Number Matches:1

74LVX86T 数据手册

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74LVX86  
LOW VOLTAGE CMOS QUAD EXCLUSIVE OR GATE  
HIGH SPEED:tPD =5.8ns (TYP.) atVCC = 3.3V  
INPUT VOLTAGELEVEL:  
VIL =0.8V,VIH =2V atVCC =3V  
LOW POWER DISSIPATION:  
I
CC =2 µA (MAX.) at TA =25 oC  
M
T
LOWNOISE:  
(Micro Package)  
(TSSOPPackage)  
VOLP =0.3 V (TYP.)at VCC = 3.3V  
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL = 4 mA (MIN)  
BALANCEDPROPAGATIONDELAYS:  
tPLH tPHL  
ORDER CODES :  
74LVX86M  
74LVX86T  
It has better speed performance at 3.3V than 5V  
LS-TTL family combined with the true CMOS low  
power consumption.  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
regard to the supply voltage. This device can be  
used to interface5V to 3V.  
OPERATING VOLTAGERANGE:  
VCC (OPR)= 2V to 3.6V(1.2VDataRetention)  
PIN AND FUNCTION COMPATIBLEWITH  
74 SERIES86  
IMPROVED LATCH-UP IMMUNITY  
DESCRIPTION  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
The 74LVX86 is a low voltage CMOS QUAD  
EXCLUSIVE OR GATE fabricated with  
sub-micron silicon gate and double-layer metal  
wiring C2MOS technology. It is ideal for low  
power and low noise 3.3V applications.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/8  
March 1999  

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