Datasheet > 74LVX74SJX

74LVX74SJX

更新时间： 2024-11-14 23:24:31

品牌	Logo	应用领域
其他 - ETC		触发器逻辑集成电路光电二极管输入元件
页数	文件大小	规格书
6页	73K
描述
Dual D-Type Flip-Flop

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数据手册

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74LVX74SJX 数据手册

May 1993

Revised March 1999

74LVX74

Low Voltage Dual D-Type Positive Edge-Triggered

Flip-Flop

Asynchronous Inputs:

General Description

The LVX74 is a dual D-type flip-flop with Asynchronous

LOW input to S_D(Set) sets Q to HIGH level

LOW input to C_D(Clear) sets Q to LOW level

Clear and Set inputs and complementary (Q, Q) outputs.

Information at the input is transferred to the outputs on the

positive edge of the clock pulse. After the Clock Pulse input

threshold voltage has been passed, the Data input is

locked out and information present will not be transferred to

the outputs until the next rising edge of the Clock Pulse

input.

Clear and Set are independent of clock

Simultaneous LOW on C_Dand S_Dmakes both Q and Q

HIGH

Features

■ Input voltage level translation from 5V to 3V

■ Ideal for low power/low noise 3.3V applications

■ Guaranteed simultaneous switching noise level and

dynamic threshold performance

Ordering Code:

Order Number Package Number

Package Description

74LVX74M

M14A

M14D

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74LVX74SJ

74LVX74MTC

MTC14

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Names

D₁, D₂

Description

Data Inputs

CP₁, CP₂

Clock Pulse Inputs

Direct Clear Inputs

Direct Set Inputs

Outputs

C_D1, C_D2

S_D1, S_D2

Q₁, Q₁, Q₂, Q₂

DS011606.prf

www.fairchildsemi.com

12 3 4 5 6

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