Datasheet > 74LVX74M_08

74LVX74M_08

更新时间： 2022-05-17 13:36:14

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		触发器
页数	文件大小	规格书
9页	320K
描述
Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop

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74LVX74M_08 数据手册

February 2008

74LVX74

Low Voltage Dual D-Type Positive Edge-Triggered

Flip-Flop

Features

General Description

■ Input voltage level translation from 5V to 3V

■ Ideal for low power/low noise 3.3V applications

The LVX74 is a dual D-type flip-flop with Asynchronous

Clear and Set inputs and complementary (Q, Q) outputs.

Information at the input is transferred to the outputs on

the positive edge of the clock pulse. After the Clock

Pulse input threshold voltage has been passed, the Data

input is locked out and information present will not be

transferred to the outputs until the next rising edge of the

Clock Pulse input.

■ Guaranteed simultaneous switching noise level and

dynamic threshold performance

Asynchronous Inputs:

■ LOW input to S (Set) sets Q to HIGH level

■ LOW input to C (Clear) sets Q to LOW level

■ Clear and Set are independent of clock

■ Simultaneous LOW on C and S makes both Q and

Q HIGH

Ordering Information

Order

Number

Package

Number

Package Description

74LVX74M

M14A

M14D

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74LVX74SJ

74LVX74MTC

MTC14

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

74LVX74 Rev. 1.4.0

www.fairchildsemi.com

12 3 4 5 6 7...9

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