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74LVT16652ADL,112 PDF预览

74LVT16652ADL,112

更新时间: 2024-11-18 14:47:07
品牌 Logo 应用领域
恩智浦 - NXP 信息通信管理光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
21页 101K
描述
74LVT16652A - 3.3 V 16-bit bus transceiver/register; 3-state SSOP 56-Pin

74LVT16652ADL,112 技术参数

Source Url Status Check Date:2013-06-14 00:00:00生命周期:Transferred
零件包装代码:SSOP包装说明:7.50 MM, PLASTIC, MO-118, SOT-371-1, SSOP-56
针数:56Reach Compliance Code:unknown
风险等级:5.7Is Samacsys:N
Base Number Matches:1

74LVT16652ADL,112 数据手册

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74LVT16652A  
3.3 V 16-bit bus transceiver/register; 3-state  
Rev. 03 — 12 January 2005  
Product data sheet  
1. General description  
The 74LVT16652A is a high-performance BiCMOS product designed for VCC operation at  
3.3 V. The device can be used as two 8-bit transceivers or one 16-bit transceiver.  
Complimentary output enable (OEAB and OEBA) inputs are provided to control the  
transceiver functions. Select control (SAB and SBA) inputs are provided to select whether  
real-time or stored data is transferred. A LOW input level selects real-time data, and a  
HIGH input level selects stored data. The circuitry used for select control eliminates the  
typical decoding glitch that occurs in a multiplexer during the transition between stored  
and real-time data.  
Data on the A or B bus, or both, can be stored in the internal flip-flops by LOW-to-HIGH  
transitions at the appropriate clock (CPAB or CPBA) inputs regardless of the levels on the  
select control or output enable inputs. When SAB and SBA are in real-time transfer mode,  
it is possible to store data without using the internal D-type flip-flops by simultaneously  
enabling OEAB and OEBA. In this configuration, each output reinforces its input. Thus,  
when all other data sources to the two sets of bus lines are at high- impedance, each set  
of bus lines remains at its last level configuration.  
2. Features  
16-bit bus interface  
3-state buffers  
Output capability: +64 mA and 32 mA  
TTL input and output switching levels  
Input and output interface capability to systems at 5 V supply  
Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused  
inputs  
Live insertion and extraction permitted  
Power-up reset  
Power-up 3-state  
No bus current loading when output is tied to 5 V bus  
Latch-up protection exceeds 500 mA per JESD78  
ESD protection:  
MIL STD 883 method 3015: exceeds 2000 V  
Machine model: exceeds 200 V  
 
 

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