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74LVT16652ADL,512 PDF预览

74LVT16652ADL,512

更新时间: 2024-11-18 14:47:07
品牌 Logo 应用领域
恩智浦 - NXP 信息通信管理光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
21页 102K
描述
74LVT16652A - 3.3 V 16-bit bus transceiver/register; 3-state SSOP 56-Pin

74LVT16652ADL,512 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:SSOP包装说明:SSOP, SSOP56,.4
针数:56Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.25
其他特性:WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION控制类型:INDEPENDENT CONTROL
计数方向:BIDIRECTIONAL系列:LVT
JESD-30 代码:R-PDSO-G56JESD-609代码:e4
长度:18.425 mm逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
最大I(ol):0.032 A位数:8
功能数量:2端口数量:2
端子数量:56最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP56,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:4.7 ns传播延迟(tpd):4.7 ns
认证状态:Not Qualified座面最大高度:2.8 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:BICMOS
温度等级:INDUSTRIAL端子面层:NICKEL PALLADIUM GOLD
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
翻译:N/A触发器类型:POSITIVE EDGE
宽度:7.5 mmBase Number Matches:1

74LVT16652ADL,512 数据手册

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74LVT16652A  
3.3 V 16-bit bus transceiver/register; 3-state  
Rev. 03 — 12 January 2005  
Product data sheet  
1. General description  
The 74LVT16652A is a high-performance BiCMOS product designed for VCC operation at  
3.3 V. The device can be used as two 8-bit transceivers or one 16-bit transceiver.  
Complimentary output enable (OEAB and OEBA) inputs are provided to control the  
transceiver functions. Select control (SAB and SBA) inputs are provided to select whether  
real-time or stored data is transferred. A LOW input level selects real-time data, and a  
HIGH input level selects stored data. The circuitry used for select control eliminates the  
typical decoding glitch that occurs in a multiplexer during the transition between stored  
and real-time data.  
Data on the A or B bus, or both, can be stored in the internal flip-flops by LOW-to-HIGH  
transitions at the appropriate clock (CPAB or CPBA) inputs regardless of the levels on the  
select control or output enable inputs. When SAB and SBA are in real-time transfer mode,  
it is possible to store data without using the internal D-type flip-flops by simultaneously  
enabling OEAB and OEBA. In this configuration, each output reinforces its input. Thus,  
when all other data sources to the two sets of bus lines are at high- impedance, each set  
of bus lines remains at its last level configuration.  
2. Features  
16-bit bus interface  
3-state buffers  
Output capability: +64 mA and 32 mA  
TTL input and output switching levels  
Input and output interface capability to systems at 5 V supply  
Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused  
inputs  
Live insertion and extraction permitted  
Power-up reset  
Power-up 3-state  
No bus current loading when output is tied to 5 V bus  
Latch-up protection exceeds 500 mA per JESD78  
ESD protection:  
MIL STD 883 method 3015: exceeds 2000 V  
Machine model: exceeds 200 V  
 
 

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