5秒后页面跳转
74LVT16952MTDX PDF预览

74LVT16952MTDX

更新时间: 2024-11-08 21:53:19
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
8页 78K
描述
Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs

74LVT16952MTDX 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:TSSOP, TSSOP56,.3,20Reach Compliance Code:unknown
风险等级:5.92控制类型:INDEPENDENT CONTROL
计数方向:BIDIRECTIONALJESD-30 代码:R-PDSO-G56
JESD-609代码:e0逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
最大I(ol):0.064 A位数:8
功能数量:2端子数量:56
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP56,.3,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
电源:3.3 VProp。Delay @ Nom-Sup:4.8 ns
认证状态:Not Qualified子类别:Bus Driver/Transceivers
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:BICMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
触发器类型:POSITIVE EDGEBase Number Matches:1

74LVT16952MTDX 数据手册

 浏览型号74LVT16952MTDX的Datasheet PDF文件第2页浏览型号74LVT16952MTDX的Datasheet PDF文件第3页浏览型号74LVT16952MTDX的Datasheet PDF文件第4页浏览型号74LVT16952MTDX的Datasheet PDF文件第5页浏览型号74LVT16952MTDX的Datasheet PDF文件第6页浏览型号74LVT16952MTDX的Datasheet PDF文件第7页 
January 2000  
Revised October 2001  
74LVT16952 74LVTH16952  
Low Voltage 16-Bit Registered Transceiver  
with 3-STATE Outputs  
General Description  
Features  
Input and output interface capability to systems at  
The LVT16952 and LVTH16952 are 16-bit registered  
transceivers. Two 8-bit back to back registers store data  
flowing in both directions between two bidirectional buses.  
Separate clock, clock enable, and output enable signals  
are provided for each register.  
5V VCC  
Bushold data inputs eliminate the need for external  
pull-up resistors to hold unused inputs (74LVTH16952)  
Live insertion/extraction permitted  
The LVTH16952 data inputs include bushold, eliminating  
the need for external pull-up resistors to hold unused  
inputs.  
Power Up/Down high impedance provides glitch-free  
bus loading  
Outputs source/sink 32 mA/+64 mA  
Functionally compatible with the 74 series 16952  
Latch-up conforms to JEDEC JED78  
ESD performance:  
The registered transceiver is designed for low-voltage  
(3.3V) VCC applications, but with the capability to provide a  
TTL interface to a 5V environment.  
The LVT16952 and LVTH16952 are fabricated with an  
advanced BiCMOS technology to achieve high speed oper-  
ation similar to 5V ABT while maintaining low power dissi-  
pation.  
Human-body model > 2000V  
Machine model > 200V  
Charged-device model > 1000V  
Ordering Code:  
Order Number Package Number  
Package Description  
74LVT16952MEA  
(Preliminary)  
MS56A  
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide  
74LVT16952MTD  
(Preliminary)  
MTD56  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
74LVTH16952MEA  
74LVTH16952MTD  
MS56A  
MTD56  
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
© 2001 Fairchild Semiconductor Corporation  
DS500103  
www.fairchildsemi.com  

与74LVT16952MTDX相关器件

型号 品牌 获取价格 描述 数据表
74LVT18512DGGRE4 TI

获取价格

3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
74LVT20 NXP

获取价格

3.3V Dual 4-input NAND gate
74LVT20D NXP

获取价格

3.3V Dual 4-input NAND gate
74LVT20DB NXP

获取价格

3.3V Dual 4-input NAND gate
74LVT20DB-T ETC

获取价格

Dual 4-input NAND Gate
74LVT20D-T ETC

获取价格

Dual 4-input NAND Gate
74LVT20PW NXP

获取价格

3.3V Dual 4-input NAND gate
74LVT20PWDH NXP

获取价格

3.3V Dual 4-input NAND gate
74LVT20PWDH-T NXP

获取价格

IC LVT SERIES, DUAL 4-INPUT NAND GATE, PDSO14, Gate
74LVT20PW-T ETC

获取价格

Dual 4-input NAND Gate