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74LVT16646ADGGS PDF预览

74LVT16646ADGGS

更新时间: 2024-11-05 13:04:59
品牌 Logo 应用领域
恩智浦 - NXP 总线收发器
页数 文件大小 规格书
21页 112K
描述
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74LVT16646ADGGS 数据手册

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74LVT16646A  
3.3 V 16-bit bus transceiver; 3-state  
Rev. 03 — 12 January 2005  
Product data sheet  
1. General description  
The 74LVT16646A is a high-performance BiCMOS product designed for VCC operation at  
3.3 V. This device is a 16-bit transceiver featuring non-inverting 3-state bus compatible  
outputs in both send and receive directions. The control function implementation  
minimizes external timing requirements. The device features an output enable (OE) input  
for easy cascading and a direction (DIR) input for direction control.  
Data on bus A or bus B is clocked into the registers on the LOW-to-HIGH transition of the  
appropriate clock (CPAB or CPBA). The select control (SAB and SBA) inputs can  
multiplex stored and real-time (transparent mode data).  
2. Features  
16-bit universal bus interface  
3-state buffers  
Output capability: from +64 mA to 32 mA  
TTL input and output switching levels  
Input and output interface capability to systems at 5 V supply  
Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused  
inputs  
Live insertion and extraction permitted  
No bus-current loading when output is tied to 5 V bus  
Power-up reset  
Power-up 3-state  
Latch-up protection exceeds 500 mA per JESD78  
ESD protection:  
MIL STD 883 Method 3 015: exceeds 2000 V  
Machine model: exceeds 200 V  

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