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74LVT16646MTD PDF预览

74LVT16646MTD

更新时间： 2024-11-18 04:47:55
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器逻辑集成电路光电二极管信息通信管理
页数 文件大小 规格书
9页 92K
描述
Low Voltage 16-Bit Transceiver/Register with 3-STATE Outputs

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中文翻译

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74LVT16646MTD 技术参数

生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP,针数：56
Reach Compliance Code：unknown风险等级：5.19
Is Samacsys：N其他特性：WITH DIRECTION CONTROL
系列：LVTJESD-30 代码：R-PDSO-G56
长度：14 mm逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
位数：8功能数量：2
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟（tpd）：5.9 ns认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
宽度：6.1 mmBase Number Matches：1

74LVT16646MTD 数据手册

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January 2000  
Revised October 2001  
74LVT16646 • 74LVTH16646  
Low Voltage 16-Bit Transceiver/Register  
with 3-STATE Outputs  
General Description  
Features  
■ Input and output interface capability to systems at  
The LVT16646 and LVTH16646 contains sixteen non-  
inverting bidirectional registered bus transceivers providing  
multiplexed transmission of data directly from the input bus  
or from the internal storage registers. Each byte has sepa-  
rate control inputs which can be shorted together for full  
16-bit operation. The DIR inputs determine the direction of  
data flow through the device. The CPAB and CPBA inputs  
load data into the registers on the LOW-to-HIGH transition  
(see Functional Description).  
5V VCC  
■ Bushold data inputs eliminate the need for external  
pull-up resistors to hold unused inputs (74LVTH16646)  
■ Also available without bushold feature (74LVT16646)  
■ Live insertion/extraction permitted  
■ Power Up/Down high impedance provides  
glitch-free bus loading  
The LVTH16646 data inputs include bushold, eliminating  
the need for external pull-up resistors to hold unused  
inputs.  
■ Outputs source/sink −32 mA/+64 mA  
■ Latch-up conforms to JEDEC JED78  
■ ESD performance:  
These transceivers are designed for low-voltage (3.3V)  
VCC applications, but with the capability to provide a TTL  
Human-body model > 2000V  
Machine model > 200V  
interface to  
a 5V environment. The LVT16646 and  
Charged-device model > 1000V  
LVTH16646 are fabricated with an advanced BiCMOS  
technology to achieve high speed operation similar to 5V  
ABT while maintaining low power dissipation.  
Ordering Code:  
Order Number Package Number  
Package Description  
74LVT16646MEA  
(Preliminary)  
MS56A  
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide  
74LVT16646MTD  
(Preliminary)  
MTD56  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
74LVTH16646MEA  
74LVTH16646MTD  
MS56A  
MTD56  
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbol  
© 2001 Fairchild Semiconductor Corporation  
DS012023  
www.fairchildsemi.com  
1234567...9

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