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74LVT126D,112 PDF预览

74LVT126D,112

更新时间: 2024-09-14 15:44:19
品牌 Logo 应用领域
恩智浦 - NXP 驱动信息通信管理光电二极管逻辑集成电路
页数 文件大小 规格书
15页 81K
描述
74LVT126 - 3.3 V quad buffer; 3-state SOIC 14-Pin

74LVT126D,112 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:SOIC包装说明:SOP, SOP14,.25
针数:14Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.21
控制类型:ENABLE HIGH系列:LVT
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:8.65 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.064 A
湿度敏感等级:1位数:1
功能数量:4端口数量:2
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TUBE峰值回流温度(摄氏度):260
电源:3.3 V最大电源电流(ICC):7 mA
Prop。Delay @ Nom-Sup:3.9 ns传播延迟(tpd):4.4 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:BICMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mmBase Number Matches:1

74LVT126D,112 数据手册

 浏览型号74LVT126D,112的Datasheet PDF文件第2页浏览型号74LVT126D,112的Datasheet PDF文件第3页浏览型号74LVT126D,112的Datasheet PDF文件第4页浏览型号74LVT126D,112的Datasheet PDF文件第5页浏览型号74LVT126D,112的Datasheet PDF文件第6页浏览型号74LVT126D,112的Datasheet PDF文件第7页 
74LVT126  
3.3 V quad buffer; 3-state  
Rev. 04 — 11 February 2005  
Product data sheet  
1. General description  
The LVT126 is a high-performance BiCMOS product designed for VCC operation at 3.3 V.  
This device combines low static and dynamic power dissipation with high speed and high  
output drive. The 74LVT126 device is a quad buffer that is ideal for driving bus lines. The  
device features four output enable inputs (1OE, 2OE, 3OE and 4OE), each controlling one  
of the 3-state outputs.  
2. Features  
Quad bus interface  
3-state buffers  
Output capability: +64 mA and 32 mA  
TTL input and output switching levels  
Input and output interface capability to systems at 5 V supply  
Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused  
inputs  
Live insertion and extraction permitted  
No bus current loading when output is tied to 5 V bus  
Power-up 3-state  
Latch-up protection:  
JESD78: exceeds 500 mA  
ESD protection:  
MIL STD 883 method 3015: exceeds 2000 V  
Machine model: exceeds 200 V  
3. Quick reference data  
Table 1:  
Quick reference data  
GND = 0 V; Tamb = 25 °C.  
Symbol Parameter  
Conditions  
Min  
Typ  
2.3  
2.4  
4
Max Unit  
tPLH  
tPHL  
CI  
propagation delay nA to nY CL = 50 pF; VCC = 3.3 V  
propagation delay nA to nY CL = 50 pF; VCC = 3.3 V  
-
-
-
-
-
-
-
-
ns  
ns  
pF  
pF  
input capacitance  
output capacitance  
VI = 0 V or VCC  
CO  
outputs disabled;  
VO = 0 V or 3.0 V  
8
ICC  
quiescent supply current  
outputs disabled;  
-
0.13  
-
mA  
VCC = 3.6 V  
 
 

74LVT126D,112 替代型号

型号 品牌 替代类型 描述 数据表
74LVT126D,118 NXP

完全替代

74LVT126 - 3.3 V quad buffer; 3-state SOIC 14-Pin
74LVT126DB,112 NXP

类似代替

74LVT126 - 3.3 V quad buffer; 3-state SSOP1 14-Pin

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