Datasheet > 74LVT126_1

74LVT126_1

更新时间： 2024-09-14 04:47:55

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
15页	90K
描述
3.3 V quad buffer; 3-state

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74LVT126_1 数据手册

74LVT126

3.3 V quad buffer; 3-state

Rev. 04 — 11 February 2005

Product data sheet

1. General description

The LVT126 is a high-performance BiCMOS product designed for V_CCoperation at 3.3 V.

This device combines low static and dynamic power dissipation with high speed and high

output drive. The 74LVT126 device is a quad buffer that is ideal for driving bus lines. The

device features four output enable inputs (1OE, 2OE, 3OE and 4OE), each controlling one

of the 3-state outputs.

2. Features

■ Quad bus interface

■ 3-state buffers

■ Output capability: +64 mA and −32 mA

■ TTL input and output switching levels

■ Input and output interface capability to systems at 5 V supply

■ Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused

inputs

■ Live insertion and extraction permitted

■ No bus current loading when output is tied to 5 V bus

■ Power-up 3-state

■ Latch-up protection:

◆ JESD78: exceeds 500 mA

■ ESD protection:

◆ MIL STD 883 method 3015: exceeds 2000 V

◆ Machine model: exceeds 200 V

3. Quick reference data

Table 1:

Quick reference data

GND = 0 V; T_amb= 25 °C.

Symbol Parameter

Conditions

Min

Typ

2.3

2.4

Max Unit

t_PLH

t_PHL

C_I

propagation delay nA to nY C_L= 50 pF; V_CC= 3.3 V

input capacitance

output capacitance

V_I= 0 V or V_CC

C_O

outputs disabled;

V_O= 0 V or 3.0 V

I_CC

quiescent supply current

outputs disabled;

0.13

V_CC= 3.6 V

12 3 4 5 6 7...15

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