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74LVT125D,118 PDF预览

74LVT125D,118

更新时间: 2024-11-06 14:40:15
品牌 Logo 应用领域
恩智浦 - NXP 驱动输入元件信息通信管理光电二极管逻辑集成电路
页数 文件大小 规格书
16页 85K
描述
74LVT(H)125 - 3.3 V quad buffer; 3-state SOIC 14-Pin

74LVT125D,118 技术参数

是否Rohs认证:符合生命周期:Transferred
零件包装代码:SOIC包装说明:3.90 MM, PLASTIC, MS-012, SOT108-1, SOP-14
针数:14Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:2.87
Is Samacsys:N其他特性:INPUTS CAN BE DRIVEN BY 3.3V OR 5V COMPONENTS
控制类型:ENABLE LOW系列:LVT
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:8.65 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.064 A
湿度敏感等级:1位数:1
功能数量:4端口数量:2
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:3.3 V最大电源电流(ICC):7 mA
Prop。Delay @ Nom-Sup:4 ns传播延迟(tpd):4.9 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:BICMOS
温度等级:INDUSTRIAL端子面层:NICKEL PALLADIUM GOLD
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mmBase Number Matches:1

74LVT125D,118 数据手册

 浏览型号74LVT125D,118的Datasheet PDF文件第2页浏览型号74LVT125D,118的Datasheet PDF文件第3页浏览型号74LVT125D,118的Datasheet PDF文件第4页浏览型号74LVT125D,118的Datasheet PDF文件第5页浏览型号74LVT125D,118的Datasheet PDF文件第6页浏览型号74LVT125D,118的Datasheet PDF文件第7页 
74LVT125; 74LVTH125  
3.3 V quad buffer; 3-state  
Rev. 06 — 6 March 2006  
Product data sheet  
1. General description  
The 74LVT125; 74LVTH125 is a high-performance BiCMOS product designed for VCC  
operation at 3.3 V.  
This device combines low static and dynamic power dissipation with high speed and high  
output drive. The 74LVT125; 74LVTH125 device is a quad buffer that is ideal for driving  
bus lines. The device features four output enable inputs (1OE, 2OE, 3OE and 4OE), each  
controlling one of the 3-state outputs.  
2. Features  
I Quad bus interface  
I 3-state buffers  
I Output capability: +64 mA and 32 mA  
I TTL input and output switching levels  
I Input and output interface capability to systems at 5 V supply  
I Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs  
I Live insertion and extraction permitted  
I No bus current loading when output is tied to 5 V bus  
I Power-up 3-state  
I Latch-up protection:  
N JESD78: exceeds 500 mA  
I ESD protection:  
N MIL STD 883 method 3015: exceeds 2000 V  
N Machine model: exceeds 200 V  
3. Quick reference data  
Table 1.  
Quick reference data  
GND = 0 V; Tamb = 25 °C.  
Symbol Parameter  
Conditions  
Min  
Typ  
Max Unit  
tPLH  
LOW-to-HIGH propagation CL = 50 pF; VCC = 3.3 V  
delay nA to nY  
-
2.7  
-
ns  
tPHL  
HIGH-to-LOW propagation CL = 50 pF; VCC = 3.3 V  
delay nA to nY  
-
2.9  
-
ns  
 
 
 

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